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Junior Physical Design Engineer
% Y; z1 \9 }( r! T; l. H/ t$ s公 司:A famous IC company
* A, }3 R; R, d7 X& n/ s- R工作地点:北京
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Position Tasks, Duties and Responsibilities
5 Z3 B/ u" i, n: e1 GThe ASIC Physical Design Engineer will: 8 K% W9 {; ?( `# [$ h; a- W
Complete third party IP integration and ensure vendor guidelines are followed.
2 s, K; q7 f7 ]. |5 F Responsible for physical verification (DRC/LVS). 6 z: g# m5 W, j; R+ }; k
IO ring design, fullchip floorplan.
]" \) h! C& l) T2 ~6 t Block level implementation.
! ~. w+ s1 ` z3 s t Work with front-end engineers to resolve problems and achieve design closure. ' ]: R! r% Z( r1 J2 Z
$ v% u, w) l* g2 b+ ]) e: u0 ]; q2 MCandidate Qualifications:
) ^5 Y# s6 Q3 t( m4 C9 j+ d0 zCandidate must: 8 q- m# S4 G9 R4 ^
Hold BSEE (MS preferred). : v, H5 C2 |6 \1 G Y/ \( b
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification : G7 O% x7 A% I1 J$ ?
Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
5 t; T; U' D5 a- r+ L Have the ability to independently identify and resolve design, tool, and flow problems.
$ Z5 U# X4 ?8 F" h Have related timing and physical concept.
& l# r# l( l8 j$ h" l Be able to design and implement physical design strategies and methodologies for deep submicron designs.
7 ?% u8 o, ]* s D4 t+ }& s) G Familiar with EDA tools. - R( H( X7 p4 E0 B
Familiar with Linux environments. 6 @6 b+ L3 O* ~9 Z6 {1 W7 {
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Any of the following is beneficial:
% Z7 A" f. g* v, _" Y b6 h STA constraint design $ H2 s' [& G% g! U) `
Equivalence checking ?RTL to gates, and gates to gates. |
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