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[問題求助] MOS承受電壓的問題

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發表於 2007-10-25 14:42:53 | 顯示全部樓層
If you can see the TSMC on-line reliability information,
& v/ j0 z) |; o1 nYou will find that there are two major fators as VDD is larger than 3.3V8 Q, f* g; w0 |5 X1 Q0 a
The first is GOI and the other is HCI.& y2 H, F! L2 q1 N6 q7 R$ L: }
GOI is related to Vgs bias, and HCI is related Vds bias.
( v+ p" f; \5 A2 Z9 [HCI issue can be improved by increase L length. Because this can reduce hot carrier effect in MOS channel., N+ [! |6 w" {
But GOI issue don't have effective to overcome it. GOI is also related to the total gate oxide area size. if you can reduce total gate oxide area size, this factor can be improved.
. X$ K0 h" H; a  M0 ^6 G6 l6 ^If you use tsmc 0.18um process 3.3 component, 3.9V may be well used.

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