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請問先進們,一個Layout電容的問題,由於小弟在畫SiG.35製程的電容時(此電容是用內建叫出來的model為"C3T_MIMW"),在跑LVS確無法驗證,出現了以下幾句文字: , i7 z) ^ l3 t f4 c
Error:No matching ".SUBCKT " statement for "C3T_MIMW" at line 26 in file "netlist"
! {# }% q2 p( p. N2 ] ' l' N9 r4 H7 o# W" y" Z% {
ERROR:source could not be read.1 e) T, {0 \. R1 e! Z% u
***calibre finished with Exit code:4***$ Q7 P8 p7 N. v
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這是netlist檔的spice:: m5 o5 p/ ~8 |( f" p+ w" o3 Z5 E2 r2 ]
.SUBCKT c1p a b
% ~" J, n, G$ C: S5 t! @" W( W *.PININFO a:I b:I# i% s/ ^8 V1 t0 X& R+ r
XC1 b a gnd! c3t_mimw c=60.07p m=10& T' S/ m f U7 B4 A5 \5 v4 H
, E5 t3 h! g4 q( F! R4 e m 麻請有了解此問題的先進們,能回答一下!! 謝謝您們 |
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