請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
( g* C' K2 r) r/ o% U要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
7 g: }# t, U$ G2 k1.
7 E/ T) @, n2 |% w, u# }, Cdesign compiler + Astro ?

- i0 F% V0 S2 Y( x  R, F+ O. W2 p# P2.
- W  `8 s4 @* T6 A+ B- usynopsys IC compiler ?

4 W! I6 V  d3 X( T3.
cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
: D" ~7 T) V& }* ?* |+ s% Z; W, e+ C4. jtag insertion by bsd compiler
7 [5 ]3 D6 }' k- t& i& M5. ICG insertion by power compiler
$ T; M' Y! Q' Q; X1 u0 r4 q  v6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
9. post-layout SI analysis by prime time si
8 c" U# @0 b/ }% w, Q! v& `10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
6 d# a  E! i2 T+ k( `2. Astro  from synopsys
) U7 H3 n" S" u" V# j( b) W3. FirstEncounter from Cadence

  ]( l1 Y/ @  T! G% Q! I6 D2 k9 AAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好