請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
* ^7 \0 P! t5 w/ j要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
1.
, n3 ]" G" y  e% c# g3 Tdesign compiler + Astro ?

2.
8 J3 }! A0 m3 p3 d; z5 @6 V5 ?! q  |" m  vsynopsys IC compiler ?
) O& ^" J4 F" p/ l. P- z
3.
cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2 }$ C4 Y7 M' R7 ~- E5 S/ w2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
1 O. E5 q. \3 \, l5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
, I! k6 S2 a+ _clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
  j$ g1 [6 A& V7 G6 u3. FirstEncounter from Cadence

; h+ |  |1 Y6 ]7 vAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好