請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
" O' f/ S. e3 f# \/ ?! |! Z要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
6 B. e/ Z5 ?- B# m$ a' X. P+ L1.
3 {$ V+ a( w) j! p7 Cdesign compiler + Astro ?
, f2 w6 E  f% k2 H5 J
, B" a4 L) ~8 v8 m3 O$ _2.
% c+ ]7 K3 A# f  s+ Vsynopsys IC compiler ?

% z$ b/ e5 T# r. R: N3.
8 n( w& C4 [* R4 v0 N8 [4 F4 ocadnece virtuso ?

lee100

Synopsys R2G flow
8 s: d4 _# _4 y8 c( M' K6 f1. rtl simulation by vcs
" h* G7 z; @3 H* d1 c1 R% R1 C2. synthesis by design compiler ultra with dc/dct mode
) u7 V3 [; y' j% y+ p+ a3. dft insertion by dft compiler
- [* t& f' p- n$ g/ P4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
1 x& F# ?2 e: v7 D8. PnR by IC compiler
: Q0 l( C7 k+ s9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
+ `: v1 x3 @6 Wclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
3. FirstEncounter from Cadence

All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好