Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes
9 L4 ^4 n" L/ ~4 L4 T
1 [4 _; n& ^. k5 F, Y/ ^" YKaran Bhatia and Elyse Rosenbaum
+ A* O" o" P5 n" H6 z. W/ oDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
# u, z) P2 l- Y0 c) Q1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu

Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
7 y, F$ X  E0 X# E5 U" |0 Binvestigated. The current compression point (ICP) is introduced to define the maximum current handling
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
$ p7 L3 @8 I" t4 I9 _0 t: VI/Os [1]. Layout-optimized ESD diodes provide a
high protection level per unit capacitance (C),
: v% H% M  J1 `( A) Lminimizing the performance degradation they induce
7 }9 a5 Y) S$ ~9 W. b0 `; Non high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼

, ?+ E3 t; q, X8 ]; h, i% a- P- z* d: [讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
4 H0 w. o$ u' o, u/ _/ _/ _, U4 X真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
4 O8 t- Z  n2 i$ d+ R2 m' V* m小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
# h+ A) b1 }' E* S. ? www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
% G) a: o0 L9 M$ @# J現在急需esd的防護方式