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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題5 B  v7 r8 l7 T% L3 A! @

8 j$ s$ e) S1 R5 x. h請教業界各位先進1 j0 F9 q+ |+ \  R$ b
目前的chip開發,需要多少投資?& m' h' U% E' H- [  V
首先是假設 Febless design house.9 z& Q$ S# g9 I; @. J2 E0 I
自家由algorithm 到 RTL simulation 完成
( g% _; Y, ]4 D0 q& T9 l$ C後端包給 backend service 公司 (layout, mask, Fab, assembly..)2 e/ d# K& g3 e: v; @& C- g3 M, _4 A
以 ARM9 or ARM11, AMBA2.0 為platform' j* W5 t" @0 |% ^& s
那麼
/ s# n) D3 ?* _5 e  (1)90奈米, NRE大概多少?
5 u+ b5 f/ [: c. {2 E! ]  (2)65奈米, NRE大概多少?6 H7 n) P; Z3 V, k3 \/ N
  (3)或是您知道其他製程, NRE大約多少..., `# a' i1 s: O

8 c$ q+ b" J6 e7 G0 `謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?1 i1 Q3 y1 ^0 o7 J0 F5 x+ r6 n9 H: o4 K& a
How many mask layers it will be?
' o; ]( X" e; M  ~3 zBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
* m0 p4 D+ |8 D) l3 F% g- k+ b& w* NHow many chips you need? A full set mask or MPW?( A0 {6 L2 U4 A/ r
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,% v% O5 X, J6 j$ o# Y, M6 i  i
3 c( a* \( S& `, p7 l
I just estimate the investiment of a ASIC team.% Z, a& `4 w5 {) m5 v2 R1 X# {
not servey for a project.
* F+ [7 w3 s% P! }So, I just want to know the range of NRE.0 v$ g, ^( u" r# d" `! v
& n. P; P" ^7 {% k* f
For example, It will be $ c/ @% F; v, V5 O/ u# z
(1) 5,000,000 NT$ ?+ Z' i. G+ |" X& P% ?
(2) 8,000,000 NT$ ?
3 t% Y7 @) a0 e8 R(3)10,000,000 NT$ ?) F7 ^# d/ \* ]8 l& I
(4)12,000,000 NT$ ?% v7 i7 X1 I) C  }' s
(5)15,000,000 NT$ ?
* G- o! u6 B, ?: t) j) A" c* O1 r5 B/ ]
Sure, I understand following things:
: p7 u, I+ N9 n8 T  a, L, u% l - full set mask cost more
2 I% Y( J+ P* g. @5 L% Y - PLL/LVDS... analog IP are extra cost
: v$ S# o  F2 v! n1 S; a$ q - pin-count and area also influence cost3 F0 g" S7 N' D% x, e1 B) B
- different package also cost different2 J1 ~! ^( w1 b5 e2 `8 D5 D

- j' [# v1 V- x9 u& y2 CTherefore, if really need information for estimate,$ s' h" y; G# A* {2 {; h
just for example.- P7 C$ }# I* {
Let's assume a SoC for FullHD TV application2 v) q7 I. l5 [+ d
it will include0 O( m, _7 U) }7 p2 @
  - ARM AMBA
3 z* L* G( }6 r1 t/ s  - DDR2 I/F
. E6 z( D2 I6 E- v7 }8 T  - GPIO, IIC,...
$ n6 y" `& s) [& H) B7 @, D  V  - LVDS out (dual link)
) p0 R% @" _& c: P: ]  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,- [0 D* o2 L9 O* i/ ]) {7 k
  - 12bit ADC, 10bot ADC x2
) }2 c+ e6 N; O4 L4 f) I/ j  - PLL/DLL/ T9 L' {5 z" j9 ?
  - 256 pins 以上
9 g( w0 v- X! m6 R0 s! m) a( n4 ]$ k1 f& ^
Than,... any idea about NRE fee?& c2 f7 J; L5 W7 J
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
6 A; D8 p3 c$ l' xbasically 65nm-->USD$1M above and 90nm-->700K above
+ Q& t9 j2 X5 Pand base on different foundry has difference price!6 O" J$ J) g  y
this price did not include any specific IP like TV encoder, decoder, vedio codec....
" S& Z/ I, |0 b2 w4 p! c# g% _' [and did not include the ARM licensee...+ u2 `; Y% \7 y
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)% i- L; Z) C8 Q: Z0 B- [
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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