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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題( y) l+ B" m( Y: _# ]" a4 Z: }
- q8 \) N* G( ~' N
請教業界各位先進
1 n, p6 V$ D7 O目前的chip開發,需要多少投資?# _( V& E) R( C' ^- A
首先是假設 Febless design house.
4 b: A" o& P6 [+ T8 @5 C/ F& ~自家由algorithm 到 RTL simulation 完成
1 T0 J  D) h3 w: _7 Q" k5 y後端包給 backend service 公司 (layout, mask, Fab, assembly..)
) b- S4 D# l( u( a2 o/ Z9 a5 M以 ARM9 or ARM11, AMBA2.0 為platform( h& ~0 m7 k. Q9 g' F  C
那麼
$ F6 l. ?1 e$ i) o* l2 [+ i, i  (1)90奈米, NRE大概多少?8 H8 [- u+ ?) R8 F
  (2)65奈米, NRE大概多少?# m( Q. A% u5 D( e7 y8 g! x
  (3)或是您知道其他製程, NRE大約多少...3 M9 ]. B, J2 @5 u9 E& l% Z

; ~$ E* j+ D) b, j# U- ~" G謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?2 b: e. }: ?4 q4 t
How many mask layers it will be?
0 a1 d* _4 z( d' DBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
; H- W/ `7 h9 W" jHow many chips you need? A full set mask or MPW?
  E+ M. y  W& s- O0 Q0 D& Q/ cWhat package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
! _* ?7 z2 S# L: j$ q' \. l: z; p- k, T' J6 I$ D: m
I just estimate the investiment of a ASIC team.
/ [1 T3 x: }, v: h% ~* I& ^: ~not servey for a project.
2 l& d1 L4 `9 l; USo, I just want to know the range of NRE.! a" f/ N! E: p" {: n
0 @+ F/ C7 n, ]' h4 L' ~
For example, It will be
9 z/ n  X8 {# t- n(1) 5,000,000 NT$ ?
0 M) C- B/ \6 G, N4 Q& T" @0 ^6 v(2) 8,000,000 NT$ ?
0 O6 y! l) P2 S; ^0 T$ I(3)10,000,000 NT$ ?
1 f' g1 q% Z6 J3 d# H9 p7 E(4)12,000,000 NT$ ?
; z& B! M# [/ W) s4 c1 }(5)15,000,000 NT$ ?- D' W, M7 A3 ?  o* A. I5 k
1 T) L+ z  D/ y- f
Sure, I understand following things:
1 O9 [. h3 I4 Y: P- Z - full set mask cost more
4 X# x% O% t7 s2 M - PLL/LVDS... analog IP are extra cost
; f: Y" M  o, c - pin-count and area also influence cost/ M* A- z- y3 C* `9 O- R+ n  c6 I
- different package also cost different
! S7 Z! s1 X3 B0 a% q7 F& x7 P4 w: |
7 N9 }; l, h) \9 g! qTherefore, if really need information for estimate,5 h+ ^/ v2 u* p9 T
just for example.; i+ Z4 U/ I# M3 d. g7 A' q4 [
Let's assume a SoC for FullHD TV application1 s2 T8 \) j- p, A- j% N( H# x$ w# {
it will include3 `8 c5 z: C4 A
  - ARM AMBA* S6 [/ \- w% R3 }% H  u) E: ~0 b
  - DDR2 I/F, j1 E6 b5 H/ q1 E4 g% @
  - GPIO, IIC,.../ S5 ^5 f1 `4 f8 V% Q% {  c7 Q; H! {
  - LVDS out (dual link)
9 x. t% Y% j& k. z  W, E( V6 q  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,( I: J5 Q( a+ B8 c: E
  - 12bit ADC, 10bot ADC x2
' g$ I5 `1 d& D6 r  - PLL/DLL, C# E# l0 E$ Q( |! M2 Y( j
  - 256 pins 以上7 A. Z$ \' A) @- p2 W3 S5 O
: N. p% s2 J% C' ?0 h3 w
Than,... any idea about NRE fee?' D. a1 K, h& T* W
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,, s0 k+ ^& B$ W5 o3 f' d5 F1 @/ m
basically 65nm-->USD$1M above and 90nm-->700K above( L* h% C. i! E3 D: `9 [
and base on different foundry has difference price!
% f4 a# l- X+ v1 K2 z2 h; o0 Xthis price did not include any specific IP like TV encoder, decoder, vedio codec....
# N2 `; e) S  ~  ]  Hand did not include the ARM licensee...
; _" [& n, w) Y2 ~  nactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer): O5 r' O0 B5 p) w5 Y: Z1 @9 N
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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