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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
* Y/ ^& J. O# f% q/ `# L
$ i" f6 y5 m. P' P; C% A請教業界各位先進4 L' G! A  @+ a8 |1 f! g
目前的chip開發,需要多少投資?, s2 t: b. X2 z% Q( y9 o
首先是假設 Febless design house.
* @% z7 C& [/ U( {自家由algorithm 到 RTL simulation 完成! m4 e: N: a" ~5 I- W( ~
後端包給 backend service 公司 (layout, mask, Fab, assembly..)
9 \8 j9 E: I' M" a以 ARM9 or ARM11, AMBA2.0 為platform
6 W/ K) m$ l3 Z0 i* o- U那麼2 X' s. J* a! Q3 ~2 z9 o
  (1)90奈米, NRE大概多少?8 C1 Y" n/ T; `- S1 t% g4 {
  (2)65奈米, NRE大概多少?, x* V$ P2 F0 @& A$ ]; r! z0 F
  (3)或是您知道其他製程, NRE大約多少...4 f( `% F! t  |5 x5 V8 g

- q% G: R, s( V! F謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
. Z% c) ^: X5 ~How many mask layers it will be?7 i" G) h% p6 q% H; s; |$ s; y
Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?. ^2 M4 K( C9 M/ s: N4 F7 }
How many chips you need? A full set mask or MPW?( y& o3 w1 U" f: U4 J; W+ g1 W1 E. u4 \
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,% s# z0 _' G' l5 V1 c$ d* \

0 p2 q/ r5 M. cI just estimate the investiment of a ASIC team.1 W5 D5 F# f6 p6 |
not servey for a project.# w# w% i+ c1 m7 @; w
So, I just want to know the range of NRE.# @  X8 N; q9 C( D/ G

$ i/ _3 Y) F4 YFor example, It will be
8 z2 q: d+ O& k6 s) B; y(1) 5,000,000 NT$ ?
7 b3 k5 x- t+ h2 a& i  B! l(2) 8,000,000 NT$ ?
0 u4 |6 @+ {  f1 b" g3 u(3)10,000,000 NT$ ?
5 V0 {- c& I% i0 r4 y; C7 W(4)12,000,000 NT$ ?" [  Z; y- [& {
(5)15,000,000 NT$ ?  y, [( H. ]/ T1 ?$ Y; i- \

1 Q2 k: k, H  _7 M& z5 n8 B( q. ?Sure, I understand following things:
. Q$ t4 m9 k( j7 E0 r5 K - full set mask cost more. N, p/ d5 [3 t
- PLL/LVDS... analog IP are extra cost( j7 F) ~+ b  Z0 N: P+ q. t
- pin-count and area also influence cost
( ^" x( [* l1 o: H* i - different package also cost different2 C* ]* V" {( K/ {& N, H9 X* D' O

( d; a5 D& X8 dTherefore, if really need information for estimate,7 R# _/ H- {* d4 G
just for example.
' x3 o+ O7 R' d- z; K" K( mLet's assume a SoC for FullHD TV application. L/ r) a* c9 s1 O, P
it will include, L+ z# n2 X0 b9 {& G
  - ARM AMBA5 E% Y% s- y$ `
  - DDR2 I/F
! M! t# }& ]' z- c* a. f  - GPIO, IIC,...# L/ A% F$ A, z% z$ W* o7 d) F
  - LVDS out (dual link)
( N5 Y( g  e0 @' b! A8 {  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
' w8 a  X3 H' ?$ i" v" _  - 12bit ADC, 10bot ADC x22 E/ {4 |6 p, ?, C% S3 R
  - PLL/DLL
. e3 d9 }7 s5 G' u  - 256 pins 以上
" P, p$ X9 r: k* H' f( O- Z  u; r, W
" r# a5 s& @; KThan,... any idea about NRE fee?
. K4 I' p! ^6 Z% iagain, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
3 k: d, K5 X. ?  ^basically 65nm-->USD$1M above and 90nm-->700K above
# k; |5 l+ M' }6 uand base on different foundry has difference price!
7 y8 I) e) k! t% p+ K+ |0 @this price did not include any specific IP like TV encoder, decoder, vedio codec....
# {+ N2 F5 b- ^- f# T* c3 ^and did not include the ARM licensee...
9 }8 o' @: P0 V  a" W3 Mactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
0 A" a  c* Z0 l2 k5 n. Z( wand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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