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Sr Analog Designer, i* e' P; k" Z: h9 O
公 司:A leader in high performance analog and mixed-signal IC design; S- T- v' H2 A1 [1 {& r- H
工作地点:北京3 T' R) C% u( }5 f* f, {5 J
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职位要求
5 \$ l0 y" \4 \9 k, [$ GEducation and experience requirement ' O2 @! t" M* B/ W! v7 O
PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design
1 w+ `; y. ~8 f/ Q! W/ L, `- Jexperience; or BS and 6+ years of analog and/or mixed-signal IC industry
; L; s/ o' f, j' y( ~% @design experience 8 I1 W; _. f" _8 v+ k) z
Hands-on CMOS product design experience in two or more of the following : f4 ?; C& b0 o# p4 `0 E
areas
9 A: g' h1 O- H7 @' u& ]* m Receiver front end, including analog front-end, demodulation, channel
% A& R6 e3 k. T) ?8 eselection etc. # y h( k- N- P! g
High-precision ADC, including sigma-delta, pipeline etc
" }0 H- S1 G- ^2 `- u High-precision DAC
1 @) I' c" ?% H! N Fully-differential continuous and discrete-time (e.g. switched capacitor) : M4 g: U7 f7 p8 w2 @
amplifier/filter design - ?1 E! x/ G: ^
High-precision oscillator/PLL/DLL
& D. j- `. T$ R Low noise voltage reference ^1 D' R0 H( H- I' h
On-chip high-voltage charge pump 7 l% Q4 p3 E t" w( `4 t
Experience in system level definition, modeling and verification a plus
9 \4 @: x7 p. ^& P6 z Hands-on experience supervising layout and post-layout verification
9 ], n4 h4 `( H: [1 B, O F: \& g Proficiency in tools ( K) r: e. Z0 U
Cadence design environment
1 t- `, j5 I, b& | Verilog/VerilogA/Matlab or other tools for system level modeling and 7 A& c' ]& r2 M4 B8 p" ?' \% c0 b
verification a plus |
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