library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分


8 a- ~% }3 ]9 h* u  pin(D) {
' u: W. S' y* S8 o1 d( t. J    nextstate_type : data;
8 ?  O( c5 w" m. D/ T    direction : input ;
" Z. y7 U3 U, L5 w    capacitance : 0.001165;
    internal_power() {
      when : "!CK";
' J! J7 i8 V5 V' J      power(POWER_7x1) {
        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }
4 c6 o2 t) o! u; d5 d7 ~
3 F( Z4 K: D" W+ evalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

    internal_power() {
  Z5 N  a' R1 z$ ]& u! Y/ Z      when : "CK";
+ C  c- X0 d) T% e# b3 f" W      power(POWER_7x1) {
8 L$ q; d, ^& t$ h) T& w/ n* {: [6 b        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
! d- u3 W) m+ z: T* k( G        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
9 w* Z8 u3 Z2 q- ~      }
    }
4 G. B6 F1 f% D' K. d    timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
4 m2 _2 `; q7 N* c- I      timing_type : setup_rising;
5 X1 J& ?, r( U* q. N      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
2 G. l1 k# t- @# _        index_2("0.006000,0.108000,0.217000");
) O* |3 K$ f( k; ?) d: s        values("0.029659,0.026470,0.036963",\
# E- n2 X$ c, v9 j3 G' Z7 Y* {               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }
% T4 \' \* d) ]+ v0 a
& n5 ]3 W- M& P3 P, X: {values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
9 s; b/ d0 m) e8 Z& D# D
1 U# Q+ v$ r* @6 X" s# P  e( c
/ a7 Y8 m7 |/ o      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
: x+ C  o9 _5 V. \        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
      }
    }

yytseng

internal_power() {
      power(POWER_7x1) {
( @9 y2 f0 U' f. s$ T7 ~        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
) `2 t" o# s$ }+ ?8 c  [===> Wrong !
===> they mean while different input slew (transition) of CK, results different internal power
* T. i& O+ s0 k$ I
! G6 B) `% g. T' p1 umin_pulse_width_high : 0.061268;
3 V: h: n  S8 i# w( C6 T6 G% Dmin_pulse_width_low  : 0.125320;
( {5 p8 T4 u0 m/ fCLK Hi/Low的長度?
====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)

( R2 Y! l( C% u0 d      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
8 n8 l6 c7 Z- K4 o  p) |    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
==> No, index1 is often input transition. here represents input slew of D pin

' N* ^; n+ l4 _$ s0 E        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
$ [. h8 m, m) @6 X6 S               "0.004917,0.000010,0.004825");
      }

) W' S2 L! u1 C" E5 a* c# {values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

  s9 J9 S) Y- T4 ^) b===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
$ C- V/ j- }6 K      related_pin : "CK";
- ^6 L2 w) _( n* U4 l" G      sdf_edges   : both_edges;
      timing_type : hold_rising;
* t8 E- K& B. j. Y+ ?( s      rise_constraint(CONST_3x3) {
/ A3 `% j! I  }; ?        index_1("0.006000,0.217000,0.434000");
' b5 |) z. l; d, S        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
0 F4 R- n( S' P/ u* \               "0.013887,0.014610,0.004117",\
, x' x  |, w; U8 ^+ Z9 d" h               "0.060728,0.056519,0.043560");
8 |9 `) c  d& X: ]% R1 c      }
9 }8 w% w* Z( f! H# u      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
               "-0.004426,0.053203,-0.004342");
+ Z" X* e+ D! V! D/ h9 l      }
    }
8 `7 H. @/ m0 q5 K  }
  pin(CK) {
    direction : input ;
  n9 z$ z1 p& g' y5 Z# _0 u    capacitance : 0.001915;
    max_transition : 0.217000;
( o2 W* U" _' K" C' v# ^    clock : true;
6 l  U2 J' _; n    internal_power() {
      power(POWER_7x1) {
  {2 I7 c) D9 B& O/ \: b        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
8 f+ D' @4 [# \0 f        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
$ j( c' @. [/ K& x      }
    }


values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

  Q  d, O2 H* [/ k4 B/ w    min_pulse_width_high : 0.061268;
7 \( O, I. o  V# Z- f6 v. t' P    min_pulse_width_low  : 0.125320;

  j; A7 {* M6 y$ ]* O7 A8 PCLK Hi/Low的長度?
  }
}



有觀念誤解的話希望幫忙修正..謝謝

[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]