library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分


/ u1 G: d/ F3 d* W: C: Y: l5 N  pin(D) {
    nextstate_type : data;
( Z5 m# h1 U+ t$ M    direction : input ;
6 p. G- G8 R# ?    capacitance : 0.001165;
& C) I: P  \1 s- F    internal_power() {
      when : "!CK";
- T% k2 k- p: R2 b' ?+ v/ n      power(POWER_7x1) {
1 v& \/ p# I/ h2 F5 ?' {        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }
: f3 B2 b, g" A7 h& {7 P
values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

. N4 B* ^. y7 a; g0 r: M$ U5 e    internal_power() {
4 U0 z- a  v  ~3 Q& D0 ?      when : "CK";
, @# c! e' j9 T- O2 f" a5 `. K$ j; D      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
      }
3 y0 W0 e1 B+ F  W8 |3 \/ _$ V% P3 g    }
$ p# Q# X+ X4 y, m7 J' k+ u1 j    timing() {
      related_pin : "CK";
3 s- F. u- w1 O0 x' B. q5 }      sdf_edges   : both_edges;
      timing_type : setup_rising;
' J7 k" u4 ]" b+ a      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
' Q, t+ i6 B& T; Y  z        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
$ Q; l6 C5 }) N# O               "0.004917,0.000010,0.004825");
      }

9 W& T* B, {, w4 R6 Xvalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
% Z7 L& I( r  a# H- h

      fall_constraint(CONST_3x3) {
/ O& O0 g) L3 b8 u8 y$ ^& _        index_1("0.006000,0.217000,0.434000");
9 c; y' W) v4 G2 i        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
/ |: R8 m" O" P3 {      }
    }

yytseng

internal_power() {
& h- n+ f9 J2 J) r7 J: S# a      power(POWER_7x1) {
$ g+ N$ B& N. x; N% O! F        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
: n, k! b# @. n) q' G! d===> Wrong !
( X3 j% l3 M1 ^0 i+ x/ x===> they mean while different input slew (transition) of CK, results different internal power
! \& x# v4 i7 E% k. g- V/ C3 W8 y
min_pulse_width_high : 0.061268;
min_pulse_width_low  : 0.125320;
CLK Hi/Low的長度?
$ T5 v* U1 v/ C2 @* f) @====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
7 @# ]7 O: [* D) ^
      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
" A: Y, Y$ F* A+ s# e+ g( c; M    }
5 C5 C; q4 D8 i. M, h, C8 `' I4 t
values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
8 ~( P8 @( K5 b, p# m==> No, index1 is often input transition. here represents input slew of D pin
; f2 k3 J: I% {: o) x
        index_1("0.006000,0.217000,0.434000");
2 p, i% l2 A, Y3 \0 z! [        index_2("0.006000,0.108000,0.217000");
/ l7 |, f1 F# q4 q+ P        values("0.029659,0.026470,0.036963",\
* K9 d3 |! x8 V, p3 q, V2 |- n; o4 K! l               "0.032032,0.023912,0.031939",\
# a  ^# U* N7 z: e4 p8 Z+ X5 {               "0.004917,0.000010,0.004825");
      }

& R# L9 `$ _0 yvalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
% l4 S7 w: o8 L( k5 L1 L6 g3 z9 ?      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
- ~. q; G2 s/ }7 {               "0.013887,0.014610,0.004117",\
               "0.060728,0.056519,0.043560");
      }
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
0 c) ?3 r7 U. ?, h               "-0.004426,0.053203,-0.004342");
8 d, e' Y7 s( X6 h5 s+ O* d2 r      }
+ P# B/ H7 d9 }. T4 s6 V    }
  @' d+ u. }% b) L( @/ L  }
  pin(CK) {
    direction : input ;
( o4 Y, [( u) j2 s0 C    capacitance : 0.001915;
7 H: Y. b3 H  i3 X$ o    max_transition : 0.217000;
0 x& x+ R  y8 y+ A8 K# R    clock : true;
    internal_power() {
      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
      }
. b6 i4 O0 R! q. @. g) {    }

- l1 q' a! {0 i  W9 Z" a9 s
- O% _; X( Q0 A' x, d6 Avalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
+ X  e) D3 g# G2 s" `9 Y/ ]
3 U5 B9 x* |. O: @* k6 ]    min_pulse_width_high : 0.061268;
    min_pulse_width_low  : 0.125320;
6 c' m1 M; B& R4 u4 f
, p$ R# O; j0 X7 Y+ C1 w8 wCLK Hi/Low的長度?
  }
  E: K. d6 L. {, H; Z}

$ x6 q+ {8 Q& q- o
! c0 S2 G5 A  h
- h- Q6 @% X) {9 ]" O( m) r有觀念誤解的話希望幫忙修正..謝謝

[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]