library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分


  pin(D) {
    nextstate_type : data;
    direction : input ;
8 V; }. B7 v, a! q) [    capacitance : 0.001165;
    internal_power() {
      when : "!CK";
, }) x$ A0 f- _$ _% I      power(POWER_7x1) {
  l4 l: C+ t" t' _        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
+ u" f1 z! B& f! z7 b8 u# i        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

! d/ U( `/ D  R+ h, G# y    internal_power() {
2 x6 w8 d* q0 e      when : "CK";
6 H! A% _, a8 Z+ ?3 q      power(POWER_7x1) {
' z8 d2 M) G* x% y( {- d: A* e+ h  I* s        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
; r$ A$ G1 O. y7 u. ?      }
: C0 A7 b+ Y: ?    }
0 Y, N# n4 b2 O    timing() {
$ ]5 m, U/ {& f' m% k# N$ q      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
) a0 g3 {2 P9 u5 @) J        index_1("0.006000,0.217000,0.434000");
- X. q4 G( i; S8 I- q        index_2("0.006000,0.108000,0.217000");
8 [$ f" q+ o. U, X7 H3 o        values("0.029659,0.026470,0.036963",\
& }  p6 W; j8 @- {9 J               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
+ P9 c2 C9 ^- N3 m5 Z- v  Q      }
7 T7 E0 {, r1 I. M% }
values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

; G0 V7 {. L, m: A' C
- @- m+ z+ [- k  l8 Q2 g- X      fall_constraint(CONST_3x3) {
# G; z- `* t' y        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
+ t/ v" `4 i/ L+ }- `+ z        values("0.074043,0.058526,0.059156",\
/ K  p- T# ~- m- ?9 U( j               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
      }
, y/ M6 Q6 @  C2 x$ v) P# Q- {    }

霜淇淋

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
* j" N1 d6 U* B' {# l. ^        index_1("0.006000,0.217000,0.434000");
; I( H) J5 k2 a: v0 j0 ?0 D! B        index_2("0.006000,0.108000,0.217000");
3 {* G& p% H1 ^        values("-0.005932,-0.005209,-0.015703",\
               "0.013887,0.014610,0.004117",\
1 S* C% W9 b. T5 x! O               "0.060728,0.056519,0.043560");
8 `  Q$ g: B0 c1 @; \, g5 a* }+ D      }
- c2 ?& P% e& v' E5 G1 [      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
5 v4 C, d, T/ c1 r        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
+ P* E* `  j% k! M1 E6 ]               "-0.004426,0.053203,-0.004342");
7 q$ o- H6 \, M8 Y, H      }
    }
. a) E% f, c# g! _% [! N* z: {+ h  }
& k+ W% f7 O0 z) B# \7 t  pin(CK) {
+ v6 [% ?- D+ r7 p% c    direction : input ;
    capacitance : 0.001915;
    max_transition : 0.217000;
" J# N9 i) L5 L. j) i# W9 K' P4 f    clock : true;
& Y& X6 Q% |2 Q9 H    internal_power() {
! x( O9 B8 X1 P* |& J  g3 h      power(POWER_7x1) {
5 n; L3 k! Y4 \+ i% T6 m        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
      }
    }
) Z0 N' s" c. m' ?3 T$ o; f
7 g. R& Q2 f  N1 D8 p0 `
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

# h+ b: v& }1 m2 f) p0 l    min_pulse_width_high : 0.061268;
    min_pulse_width_low  : 0.125320;

& x' g7 }; x  C! [# G8 UCLK Hi/Low的長度?
7 K3 b/ |* u! t$ P( _6 g  }
' f' w& V9 v: M/ o- ?2 I' g, M# `}
( `/ Q. K; y2 i7 b# b; O/ d


! R9 X. B( t8 U9 O2 V4 |有觀念誤解的話希望幫忙修正..謝謝
3 l  h- P; ]  u( _+ C! V+ e
! R! J8 T! g& P1 G$ T! N[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]