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補充:2 v& c, S$ i* w. ^
1. Reference Library: the reference libraries or Process Design Kits (PDK) where the symbol views of master cells are present. 既你想要用的symbol是來至哪個 library.6 w3 K5 d) \4 i( h5 ^
2. Syntax for Specifying Device Maps in a Device-Map File:+ t( ~( ~/ K5 [+ M- P9 M X! I4 u
devMap := <primitive_device_name> <mapped_device_name>
7 j: p8 R! ~, \5 X0 Y) h- E; m [ propMatch := list_of_prop_to_match ]9 s( q7 c3 ^9 m B
[ termMap := list_of_terminals_to_map ]/ t1 `. v+ d% b0 l- @# F& N
[ propMap := list_of_properties_to_map ]
6 h `. @4 E: _* L [ addProp := list_of_additional_properties_to_map ]
0 g% [% s* s7 p Example:: n4 D/ o+ s: R/ Q4 M8 H3 A
devMap := resistor res6 e6 K+ E# \3 g
propMatch := r 20000
! _ N. f& p4 } termMap := PLUS PLUS MINUS MINUS
. c0 ~ X5 N: m! Z* p3 b S* G propMap := subType type r resVal w width l length
8 k3 y. n+ d/ i ~. b addProp := model res |
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