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[好康相報] 10/15 Apache Technology Forum 2010

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發表於 2010-10-4 16:23:00 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
Date: October 15, 2010 - October 21, 2010
# D8 J8 A% N* |" m5 ELocation: Taiwan, Japan, Korea
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) ?& @9 n. `6 }2 N2 w) x. ~  D7 x, a! LPower Methodology from RTL Design to Chip-Package Sign-off
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In this full-day multi-track technology seminar, Apache Design Solutions, along with industry leaders, will share proven methodologies for addressing the most critical design challenges faced by engineers today – power and noise management for electronic designs. Presentations include technology roadmap for 28nm processes and beyond, advanced reliability solutions for electrostatic discharge (ESD) and dynamic electro-migration (EM), and 3D-IC design impact on power, signal, and thermal integrity. Afternoon tracks provide in-depth technical discussions on two key requirements for design methodology – achieving ultra-low power design targets while maintaining design integrity, and meeting system cost and performance needs through integrated chip-package-system design flow. Both presentations will walk the audience through a complete flow using real design examples to provide practical use information that can be applied to their current design projects.
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Taiwan
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