When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. , C9 S) V. g' O1 h, u" gIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace?" `1 n% }% U. | v1 J7 c
Thanks
u r proposed to refer to 3W rule. # }( X. E: ], S: c) G% o
when clock trace is 5 mils, u will need 10 mils spacing. ' P: ]' |, n& |: {+ o5 rof course GND trace will help, but PTH through holes with proper interval will do it better. 1 j6 d2 A5 x1 n5 o2 n ' X% u# B. p, \google it for detailed information, please!