When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.: E6 s. d+ Z8 Y* |/ o/ E7 k
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? + w; v) x2 A- a# a; d" mThanks
u r proposed to refer to 3W rule. 1 j+ r, R7 \! I7 Awhen clock trace is 5 mils, u will need 10 mils spacing. 4 L. l, O" P7 ?of course GND trace will help, but PTH through holes with proper interval will do it better. 9 F7 h+ X: G6 z- u9 D6 q1 ^" s. U: q+ k
google it for detailed information, please!