When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. ) |4 i$ r1 v4 R2 o c, \Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? & B2 X7 O. \8 G+ @Thanks
u r proposed to refer to 3W rule. ; l& H( q U0 v8 S0 c; ]9 n2 Z
when clock trace is 5 mils, u will need 10 mils spacing.' s+ g1 R0 r1 z$ M
of course GND trace will help, but PTH through holes with proper interval will do it better.% ~: W4 J8 O- N) Z& b; W
$ f/ |& P' h3 F* S: ]3 c0 \google it for detailed information, please!