When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. + z! t. B% j# \1 D( E2 RIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace?% `" O/ h0 E% j) s
Thanks
u r proposed to refer to 3W rule. ; W6 L5 l! O+ N2 r* C* g0 [ Gwhen clock trace is 5 mils, u will need 10 mils spacing." U3 s$ b% `4 b
of course GND trace will help, but PTH through holes with proper interval will do it better. ) T3 J" g: q8 J# `) y$ \ ; h# l; \4 X# _' t! K4 Y/ `google it for detailed information, please!