There's a career in Analog/Mixed-Signal? Where's A/MS Talent in Taiwan?

globe0968

聘公司：one famous IC company
2 Q+ M% j1 G7 N: R1 t4 l% ?招聘岗位：Sr. Design Engineer
0 X% e# [6 l: |& _& ~工作地点：Shanghai
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岗位描述：
-Work with analog power IC design team for new product development; -Work closely with layout designer for layout implementation -Verification of performance requirements using appropriate simulation and verification tools. -Support test & product team with chip debugging, failure analysis, characterizations and product release efforts;
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; x0 |3 ~1 R3 T* M* \' W职位要求：
-Master degree or above in EE or related field; -3+ years of working experience on analog power IC design area; -Familiar with details of product development: design method, design process, CAD tool, design for test, physical design, system applicant -Strong experience in power analog blocks design, including LDO, DCDC Converters, Battery Charger, WLED Driver, Power Path, Charge Pump, etc. Especially on switch mode converter designs. -Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator), Virtuoso; -Understanding of BiCMOS process technologies and device physics -Excellent understanding of written English and good spoken English -Good communication skills and cooperative spirits. -Outstanding ability of self-management and attain goal under pressure.

ranica

招聘公司：A communications chip company
招聘岗位：内部审计
, ~: h2 r1 w% u  [工作地点：Shanghai
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岗位描述：
工作目的和性质：在审计监察部经理的领导下，开展与内控管理相关的组织、协调的相关工作，负责组织对下属分、子公司的审计监查组织工作。 主要职责： 1. 对内部控制及风险管理的有效性进行评审，推动建立、健全内部控制系统。 2. 制定公司内部审计制度，负责审计项目的调查，拟订具体审计方案，出具审计计划与审计通知； 3. 编制审计工作底稿，并收集、整理和归档各种审计资料； 4. 对被审计单位财务收支及其他业务活动的真实性、合法性、合理性、效益情况进行独立的经济检查和监督； 5. 实施审计调查，控制、考核、纠正被审计单位偏离公司整体经营目标的行为； 6. 编制审计报告并就审计结果对财务及经营管理提供有效、可行的建议； 7. 开展内控审计，对公司内部控制制度的建立与执行情况进行审计； 8. 参与经营管理方面的内部控制程序和制度的制订； 9. 综合管理部/审计监察部经理安排的其他工作。
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职位要求：
任职要求： 1. 学历要求：全日制大学财务、审计类专业本科以上学历，持有CIA资质者优先考虑。 2. 工作年限：8年以上企业内部审计监察工作经验 3. 其他要求： a) 坚持原则，廉洁奉公，忠于职守； b) 有较强敏锐的洞察力、逻辑分析能力以及较强的持续学习能力，富有创新意识； c) 熟悉财会、税收等相关经济法律法规，熟悉企业内部控制与经营管理；熟悉内部审计的规范、程序，了解企业风险管理与控制； d) 优秀的文字表达能力； e) 熟悉应用各类办公软件； f) 良好的沟通与团队协作能力，良好的亲和力和应变力； g) 具有较强的自我学习能力和独立开展工作能力； h) 积极主动，能在压力下工作。

ranica

招聘公司：digital audio chip maker
6 b  }; h6 i* C+ `& k$ l招聘岗位：模拟IC设计工程师
工作地点：Shanghai
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, Z  S( Y3 z8 ^5 k5 Q岗位描述：
岗位描述： 1. 设计模拟电路或混合信号IC。 2. 使用CADENCE或MENTOR GRAPHICS设计工具进行模拟电路设计，仿真。 3. 设计版图布局，并协助版图工程师进行版图设计，确保版图达到电路设计的要求。 4. 计划实验室评估计划，并使用实验室测试设备对工程样片进行测试评估。 5. 撰写设计，测试报告,协助测试工程师进行中测和成测规范的定义和程序开发，验证。

5 q# B0 K' p% ~0 P& o! E) E0 |职位要求：
职位要求： 1. 具备扎实的电子电路和晶体管的理论基础，掌握IC设计流程、方法及工具，熟悉集成电路制造过程和工艺。 2. 熟练应用Cadence设计软件进行IC设计。 3. 熟悉模拟电路的原理，设计技巧及关健参数，如参考电压源，振荡器，放大器，比较器等。 4. 具有良好的学习，分析和创新能力，良好理论与实际结合的能力，在电子电路方面有良好的悟性。 5. 具有模拟或混合信号IC成功量产经验 、硕士研究生或以上学历。

ranica

招聘公司：a fabless IC design company
招聘岗位：Junior/Senior VLSI Designer
4 Q8 w4 R' t5 b- Z! R  G5 T工作地点：Shanghai

岗位描述：
Responsibilities: 1. Chip level micro-architecture design for digital TV and Set-Top-Box applications. 2. RTL level design and system simulations. 3. RTL to netlist synthesis, formal verification and timing analysis. 4. JTAG boundary scan and full scan chain implementation as well as ATPG vector generation.
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: ^9 j) g: F/ W' J. Y职位要求：
Requirements: - BS or MS degree in EE with 3+/5+ year VLSI chip design experiences. - Skills and experiences in DTV SOC design, computer system, 2D/3D graphics, digital audio DSP processor and/or networking chip designs. - Experience in RTL simulation tools, Synopsis logic synthesis tools, Formal verification tools, timing analysis tools, and Design-For-Test schemes. - Knowledge and technical background in one or more of the following areas are necessary: Computer architecture, PCI bus, USB, ATA bus, IR, UART, SmartCard, 1394, Ethernet, DDR, SDR memory systems will be helpful - Good communication skills and self-motivation!

ranica

招聘公司：A famous IC company
招聘岗位：CEO Assistant & PR Specialist
工作地点：Shanghai

岗位描述：
General Purposes / Objectives 总的目标协助 CEO 处理日常及商务事项，负责公司与政府、行业关系工作 职责范围 CEO Secretary 1.负责总裁日程安排，协助总裁处理日常办公，商务事项 2.整理会议纪要、草拟报告文件及相关文档的建立 3.负责总裁各级文/函/电的处理，协助总裁对外各项沟通和联系工作，包括与投资方的沟通协调。 PR Specialist 1.处理与政府相关部门的联系，为公司争取相关的政策与资金支持及申报 2.处理与行业协会的关系，为公司收取相关行业动态及协会支持

职位要求：
Position Requirements 职位要求 Education 教育: 本科以上，CET-6 Experience 经验10 年以上相关工作经验；至少5 年以上半导体行业相关经验 Specific or Entrepreneurial Knowledge 特殊技能对外沟通协调能力优秀，英文听、说、读、写能力优秀

ranica

职位要求：
Job Specifications:
1. BA degree or above in telecommunication, electronic engineering or microwave, etc.;
: |" n% q4 c" [7 v$ L. B2. RF sub-system design and production experience within the mobile communication industry;
3. Ability to read and understand the 3GPP specification in general and the air interface in specific;
4. RF Knowledge in modern wireless communication and communication theory;
# I; j; R8 u9 Z2 Y/ c; B5. Circuit theory knowledge and experiences in RF and microwave;
& x: N1 I0 W. ^: b6 S2 N6. RF instruments handling such as spectrum analyzer, RF signal generator, noise analyzer, vector network analyzer, VSA, etc.;
) F0 h$ K( a4 d; _# K7. Lab work skills (handling 0204 components e.g. when matching the RF parts);  
8. Skills in Schematic drawing; 9. Fluent English in writing and speaking.

ranica

招聘公司：A famous IC company
% x: I( v& g, B4 C) z招聘岗位：(Senior) RF HW Design Engineer—— Mod/RD/HWI
工作地点：Beijing

9 S; v7 {0 {$ e$ M6 o6 P岗位描述：
  B% X+ Q: e# @) a+ r# QKey Responsibilities:
1. RF sub-system design through close co-operation with Baseband to develop HW platforms for R&D SW development;
; _8 j7 q/ }, X2 D3 k3 l- }- |2. RF sub-system design through close co-operation with Baseband to develop effective robust reference HW modem design, which can be used for customers’ mass production;
3. RF Block Diagram, Link Budget Calculations, Design specification documentation, Schematic drawing, PCB layout review, etc.;
4. Specifications of RF front end components like duplexers, filters, switches and power amplifiers in cooperation with component suppliers;
5. Components evaluation, first reference design builds;
6. Test and verification of RF transmitter and receiver blocks on the reference design;
' c* s) r+ z$ r* m7 ~7. Deliver efficient methods for production calibration and test to customer production;
1 W. T  A3 |/ N+ s0 E) a8. RF new technical track and study;
9. Technical support and customer trouble shooting in RF; 10. Support Customers to develop production environment calibration and test.

globe0968

招聘公司：Access network products company
招聘岗位：方案经理
工作地点：Shanghai
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岗位描述：
2 m; y& [7 y' a$ O+ f9 [8 W1、针对有线电视运营商（MSO或有Cable网络运营商）规划解决方案，含战略/业务规划、需求管理、路标制定、架构设计等，能够抓住客户的转型方向、全业务转型的机会窗，提升公司解决方案和产品的商业竞争力； 2、理解广电客户对业务及集成需求点，并依此设计满足完善的技术解决方案，推动公司相关部门实现解决方案并在目标客户成功落实实施、响应及支持方案和合同项目执行中所需的客户需求和沟通交流； 3、负责面向MSO客户的融合业务解决方案规划，包含但不限于 HFC / EPON / 融合通信等领域的方案战略； 4、负责面向MSO客户的网络演讲解决方案规划，包含但不限于CATV / EPON / EOC, 综合接入，家庭网络等解决方案；

: T7 B/ G$ a0 g, U7 o职位要求：
$ f9 D: K2 l/ b9 }0 y2 `1、学历:本科以上，电子、广播电视、通信、计算机等相关专业； 2、经历要求:5年广电行业经验，有实际的广电系统集成经验者优先考虑，对广电业务中常用的网

globe0968

招聘公司：Access network products company
招聘岗位：方案经理
0 t, ]) K$ w; [/ \1 e工作地点：Shanghai
4 A2 s7 C: O; b4 O
岗位描述：
1、针对有线电视运营商（MSO或有Cable网络运营商）规划解决方案，含战略/业务规划、需求管理、路标制定、架构设计等，能够抓住客户的转型方向、全业务转型的机会窗，提升公司解决方案和产品的商业竞争力； 2、理解广电客户对业务及集成需求点，并依此设计满足完善的技术解决方案，推动公司相关部门实现解决方案并在目标客户成功落实实施、响应及支持方案和合同项目执行中所需的客户需求和沟通交流； 3、负责面向MSO客户的融合业务解决方案规划，包含但不限于 HFC / EPON / 融合通信等领域的方案战略； 4、负责面向MSO客户的网络演讲解决方案规划，包含但不限于CATV / EPON / EOC, 综合接入，家庭网络等解决方案；

* L2 H# G! y% q4 f  j" R职位要求：
1、学历:本科以上，电子、广播电视、通信、计算机等相关专业； 2、经历要求:5年广电行业经验，有实际的广电系统集成经验者优先考虑，对广电业务中常用的网

ranica

职位要求：
0 E4 u' R% i4 o! zPerson Specification Qualifications Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience. Experience · Minimum of 3 years industrial experience · Strong C/C++ coding and debug skills – preferably using GCC, XX’s compilation tools, or MS Visual C++ · Experience of developing with 3D and/or 2D graphics APIs, ideally OpenGL ES/desktop Open GL/Direct3D and/or OpenVG · A good understanding of the interaction between software and hardware · Experience of microcontrollers/microprocessors · Experience of interacting with colleagues outside of China Desirable · Professional experience of customer and sales interaction – ideally in a Technical Support role - as well as development work · Knowledge of XX processor architectures · Knowledge in GPGPU, ideally OpenCL · Device driver development experience, ideally in Linux/Android · Development experience in windowing systems, for example X11 in Linux · SoC design experience, including development of synthesizable Verilog/VHDL modules Personal Requirements · Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English · Must be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner · Must have the desire and ability to solve problems quickly · Must be enthusiastic and well driven · Must be able to schedule own workload and plan tasks – based on both internal and customer requirements. · Must have good inter-personal skills, and be able to work well within a team; especially when under pressure · Must be willing to be flexible and accept new challenges · Must be able to travel on a regular basis, both to give customer training

ranica

招聘公司：A famous IC company
招聘岗位：Software Applications Engineer - Graphics
4 L" x! R' f, ^+ g- Z0 w工作地点：Shanghai

& j* F# A0 _- X+ Y# u& r' N岗位描述：
Background XX’s Application Engineering Group is responsible for providing high quality technical support to customers using XX’s products. In order to do this, we have a number of Applications Engineering teams based at various locations around the world. We are now looking for someone to join a small team based in our Shanghai office. This role will encompass the provision of high quality technical support as part of a co-ordinated worldwide team. Applications Engineering role You will be required to gain a good knowledge of XX’s processor cores, GPUs, development tools/boards, and other products through close working with the worldwide application engineering teams and XX's Product Engineering group. Then to use this knowledge to provide XX's customers with the assistance they require to develop systems around the XX processor and XX GPU contained within their new products. The transfer of your knowledge will take a number of forms. Firstly, you will need to be able to provide comprehensive responses to customer enquiries. Such enquiries may be received by email, telephone or face to face meetings. Secondly you will be required to provide in-depth technical training to XX's customers. You will therefore be expected to be able to travel every six to eight weeks. You will also be expected to have excellent interpersonal skills and be a good presenter. Thirdly you will be responsible for the generation and review of new product documentation, such as application notes, frequently asked question lists and user guides. This may include translation for local language support. Finally, you must be reactive to the demands of both customers and sales and feedback requirements to XX’s Engineering and Marketing groups.

ranica

职位要求：
Experience: The person for this position will need the following abilities - Strong technical account management and project management skills - Strong PCB knowledge including schematic design and layout. Hands-on skills of PCBs including prototyping and optimization board design. - Strong HW development, debugging and troubleshooting capability - Basic SW programming skills. Able to review basic C/C++ code and provide driver integration support - Customer field trial experience - Extensive knowledge of tuner/demodulator/decoder in system and application levels - Test equipment operation: Spectrum analyzers, network analyzers, signal generators - Must be able to communicate clearly and have good customer interface skills. Qualifications: - BSEE with 7 years or MSEE with 5 years in RF/Mixed signal IC systems engineering or applications engineering. - Tuner/demodulator/decoder hardware/software experience and familiarity with high volume consumer oriented RF IC’s.

ranica

招聘公司：A famous IC company
/ {- U2 ^  K3 f; w3 r' R% ^招聘岗位：Senior Application Engineer
0 Y4 E0 s% r' Q+ ?# M0 m0 g工作地点：Shenzhen
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% s0 ]0 ?& R7 b- g' O7 b3 u4 L岗位描述：
The candidate filling this position needs to be an experienced systems/application engineer with extensive tuner/demodulator/decoder knowledge in both hardware and software areas. The main job function includes o Design and support reference designs o Manage strategic partner accounts o Work with local FAEs supporting alpha customers during early product roll-out phase. HW (RF and base-band) design/debug skills are a must while basic software programming skills including driver integration and writing ATEs for reference design testing is highly desired. The preferred applicant will have extensive knowledge of tuner/demodulator/decoder in both system and application level. Previous experience of supporting IC product into high volume shipment is a must. The ability to establish and maintain good partner relationship as well as good technical project management skills is a must Job Description: Primary responsibilities will include: - Supporting strategic partners/alpha customers by reviewing, testing and debugging reference designs. Provide HW & SW driver integration support. This requires up to 30% travel to partners/customers in China - Define design, debug, and characterize reference design EVKs - Generate application note and test report - Manage and provide technical support to multiple strategic partner accounts - Collect market and competitor information for marketing analysis - Travel to US headquarter for product support training as needed

ranica

招聘公司：A famous IC company
招聘岗位：Senior mixed signal verification designer
工作地点：Shanghai

岗位描述：
, O5 Q: r& h9 p+ ]6 a0 k* N+ F- j% nDescription of Function & Responsibility 1) Design digital behavior model for SOC analog IP, such as transceiver, PLL, high speed SERDES, etc. 2) Build simulation environment to verify digital behavior model. 3) Build mixed signal simulation environment to do Verilog-Spice verification. Check mixed signal simulation results with behavior simulation results to correct model. 4) Extract analog IP timing information and verify.
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! f# f; s& s( |4 b/ _$ K2 W职位要求：
Education: MS or above in Electrical / Electronic Engineering. Experience: Master with 4+ experience with emphasis in mixed-signal, digital integrated circuit design. Familiar with Verilog coding, digital verification, mixed signal verification and the use of various design CAD tools such as VCS, NC-Verilog, HSPICE, Spectre, etc. Familiar with SOC chips, knowledge of memory, PLL, ADC, DAC is preferred.

ranica

招聘公司：A famous IC company
招聘岗位：Sr. Staff engineer, Analog/mixed signal IC design (wireless team)
工作地点：Shanghai

岗位描述：
! f+ ^5 S# K1 o0 uJob Description: Our mixed-signal team develops cutting edge technology for the wireless product line. We are actively seeking talented analog design engineers who want to join a dynamic and experienced team and take their technical knowledge to the next level. This job involves working closely with US team in developing and eventually supporting the production of next generation sub-micron mixed-signal blocks. Responsibilities: - Technical lead of the wireless team in China designing analog blocks such as PLL, ADC, DAC, Filter, Regulator, SERDES - Corner Simulations (Cadence, Spectre, Ocean, Monte Carlo, ADS) - Layout design - Block/chip level verification (LVS, DRC, LPE) - Design review - Chip level integration - Test, characterization, debug - Close work with US team including occasional travel - Helping other team members with their design/schedule

3 w1 f. }3 X0 [) a( [职位要求：
Job Requirements (education and experience): - MSEE with at least 10 years of industry experience - Previous leadership experience is a plus - Deep understanding of fundamental analog techniques - Experience with low-power analog design in deep submicron CMOS - Experience in Cadence Spectre, SpectreRF, AMS and Virtuoso - Hands-on experience in analog layout design and verification - Knowledge of Skill, Matlab & verilog programming - Experience with high volume IC manufacturing is a plus - Hands-on experience with lab equipment - Occasional travel to US for technical training/design review/product test

ranica

招聘公司：A famous IC company
2 d2 F: M6 [% u4 B+ T. w# }招聘岗位：Senior System SW Engineer
工作地点：Beijing
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岗位描述：
1 f: s$ Q  V* a$ P# @  ~+ PJob Description: 1. Involved in multi-mode protocol stack(GSM/GPRS/EDGE/TD-SCDMA/TDD-LTE) requirement analysis, design and tracking 2. Involved in multi-mode protocol stack(GSM/GPRS/EDGE/TD-SCDMA/TDD-LTE) architecture design and interface design 3. Follow 3GPP/CCSA standard evolution; 4. Modem platform software requirement analysis and architecture design; 5. Modem platform software trouble shooting and performance optimization; 6. TD-SCDMA Dual SIM Dual Standby platform requirement analysis and architecture design; 7．Cooperate and communicate with technical design teams to achieve modem platform software development;
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职位要求：
4 L5 _3 n5 f3 ?6 {/ p( t; fJob Qualification 1. Master or above of Telecommunication, electronic engineering, Computer Science or Automation relevant field; 2. Familiar with wireless communication technology (LTE/TD-SCDMA/WCDMA/GSM/EDGE); 3. Experienced with embedded software programming C, C++. Familiar with Multitasking RTOS environment; 4. Familiar with ARM development tools and debug methods. 5. Strong proficiency in mobile phone platform architecture design. Have knowledge of some mobile phone components(RAM/FLASH/LCD/Keyboard/Power/USB/UART/SPI/IIC/GPIO……); 6. Prefer experience of mobile phone platform architecture design or driver development; 7. Excellent communication and organization skills; 8. Good ability in English for technical reading and writing, fluent in English communication;

ranica

招聘公司：A famous IC company
招聘岗位：Senior mixed signal verification designer
工作地点：Shanghai

岗位描述：
Description of Function & Responsibility 1) Design digital behavior model for SOC analog IP, such as transceiver, PLL, high speed SERDES, etc. 2) Build simulation environment to verify digital behavior model. 3) Build mixed signal simulation environment to do Verilog-Spice verification. Check mixed signal simulation results with behavior simulation results to correct model. 4) Extract analog IP timing information and verify.
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职位要求：
5 ]5 Z7 t# p. mEducation: MS or above in Electrical / Electronic Engineering. Experience: Master with 4+ experience with emphasis in mixed-signal, digital integrated circuit design. Familiar with Verilog coding, digital verification, mixed signal verification and the use of various design CAD tools such as VCS, NC-Verilog, HSPICE, Spectre, etc. Familiar with SOC chips, knowledge of memory, PLL, ADC, DAC is preferred.

ranica

Responsibilities: - Technical lead of the wireless team in China designing analog blocks such as PLL, ADC, DAC, Filter, Regulator, SERDES - Corner Simulations (Cadence, Spectre, Ocean, Monte Carlo, ADS) - Layout design - Block/chip level verification (LVS, DRC, LPE) - Design review - Chip level integration - Test, characterization, debug - Close work with US team including occasional travel - Helping other team members with their design/schedule
6 b, N+ J( K. z% S) i2 C4 t; r
" k& O9 x  j, y5 a6 h0 F职位要求：
Job Requirements (education and experience): - MSEE with at least 10 years of industry experience - Previous leadership experience is a plus - Deep understanding of fundamental analog techniques - Experience with low-power analog design in deep submicron CMOS - Experience in Cadence Spectre, SpectreRF, AMS and Virtuoso - Hands-on experience in analog layout design and verification - Knowledge of Skill, Matlab & verilog programming - Experience with high volume IC manufacturing is a plus - Hands-on experience with lab equipment - Occasional travel to US for technical training/design review/product test

ranica

招聘公司：A famous IC company
招聘岗位：Sr. Staff engineer, Analog/mixed signal IC design (wireless team)
工作地点：Shanghai
' E  V& s0 t& J2 l$ ~' z
/ c" j8 ?% \5 w岗位描述：
Job Description: Our mixed-signal team develops cutting edge technology for the wireless product line. We are actively seeking talented analog design engineers who want to join a dynamic and experienced team and take their technical knowledge to the next level. This job involves working closely with US team in developing and eventually supporting the production of next generation sub-micron mixed-signal blocks.

ranica

Duties and Responsibilities

% e0 v$ c% m1 g4 N9 c. n1. Responsible for PKG NPI Process Set-up (including cost reduction, new material development and new process development) in the area of Solder die attach (soft solder die attach, paste solder die attach, epoxy die attach), Reflow soldering and cleaning, Heavy Al wire bond (5-20 mils wire) , Au wire bond and Cu wire bond.
- H# Q* i2 x( ~  a4 ~+ k2. Responsible for process characterization and improve process capability based on 6sigma process capability.
3. Responsible for co-work and hands over to process engineering on process set-up results according to APQP procedure based 6sigma process capability.
6 F( O/ n8 k) A/ F) M3 z1 N8 @4. Responsible new process equipment selection and evaluation to communicate with equipment engineering with right comparison of COO
5. Benchmarking one new process and new Process Development that does not exist and outside design Rule by Co-work with Dev. Engineer and process engineers
2 Y: o% D  d- o  H2 j2 j% u+ I# \, @6. Conduct PA work following Advanced Product Qualification Plan (APQP) Spec, FSC-QAR-0013.
' S6 q0 d5 |$ |  L- J7. Responsible for deliberative package development, Major Tool Change (Mold die etc) to improve quality and In-sourcing project that is new
8. Holding technical leadership for process development working with project members such like Industrial Engineering, SCM, Purchasing, Process Engineering, QA, Program management, Human resource, Facility, and manufacturing.
1 l8 T4 f- s; R7 }3 W9. Study and understand customer requirements, application, EHS and design those things to the process development.
10. Supporting development engineers to generate and create documents deliverables such as control plan, process FMEA, LAR plan, project charter, Quality function development, project schedule, line certification plan, to identify process development cost, etc.
11. To plan and execute process optimization, failure analysis, process characterization, samples build for the development.
12. To lead project team members related with process development.
1 ^) U( k4 e; `2 Z! [6 x/ U) w13. To find technical and systematic solution for failures of reliability, quality, manufacturability, cost, and cycle time that are related with process. 14. Track team member performance and report to origination manager
" P/ k: p+ g$ I. L' f15. To share and update project progress, risk of delay, constraints, weekly at designated day with stakeholders, project team, sponsors.