|
Senior Physical Design Engineer4 _4 L8 s/ f: m) s% `7 f0 N
公 司:A famous IC company3 c6 W: ?. s3 r! ~9 ^0 [' r
工作地点:南京
' N; T, J3 Q5 \1 V9 G6 ~) a) h
! Z' t$ U7 r- M( l+ s2 K% L9 NKey Responsibilities
3 `- {( w0 B2 y/ |& \: w3 A. LDepending on experience, key responsibilities will involve some of the following: 5 p |; F& n w5 e
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. $ e# L2 c2 M/ ?4 u9 ~, j1 e) E
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
* H) D/ v j& W& |' P6 bLeading a team of physical design engineers and resolving the technical related issues.
A1 ~; Z! V0 m$ O# [Crosstalk analysis, power analysis, and static timing analysis.
9 T+ x. `9 R, w+ b- tWrite scripts in Tcl to improve productivity. % P4 Q( a9 v2 U, T( p
/ ?, R5 j2 [5 Y1 [1 DExperience: 5+ years in physical implementation engineering
# o$ y* ]; j S
+ M6 x1 b: h1 q3 o% X* {9 GEssential skills
6 I9 }* }: ]: tMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills $ H- A0 P( j, ?( e+ b3 J
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. * q) j3 F5 r9 g8 k# ^9 y
Good programming skill. Capable of writing Tcl or Perl.
* M5 m7 u( n4 e4 W$ J; K' U1 iFamiliar with synthesis, static timing analysis.
1 }5 I& f# F4 RSelf-motivated team worker, good verbal and written communication skills in English.
, c2 ?6 v& R! j& T8 OTechnical and team leadership proffered. Previous management experience highly desired.
2 r8 N1 m+ w# q* q" q9 UExperience with synthesis, DFT, and verification is preferred. |
|