FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer
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/ L7 W" L. p; H2 Q0 j$ K2 F公      司：one famous IC company
工作地点：上海

8 X$ W6 q/ f- Y1 VQualifications
+ b* O. V4 k  Q7 ^+ N* GMS in EE/CS/ME.  
" R) z7 e! B2 a: ^Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
" T* k: ]# t5 ICandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
, Z( r. F; d- p9 W, Y; lGood knowledge ddr protocol and computer system achitecture would be an added advantage.
' ]6 `1 ]( _( }" z! K' D5 tGood knowledge of Perl and shell programming would be an added advantage.  
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Responsibilities:
! `: ~* ^) V8 Z( @% g' R* ]3 d; n6 R/ f-Understanding the expected functionality of designs.
-Developing testing and regression plans.
: i0 z4 d+ a) H2 c4 ~) K8 Y, o-Designing and developing verification environment.
2 Q1 i! ?* b6 b2 h1 m* a1 h8 |% d8 E-Running RTL and gate-level simulations/regression.
6 B! A9 i, k2 p8 d7 e% _, A-Code/functional coverage development, analysis and closure.

: a: M* `+ B8 iRequirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
! Q1 E' D$ G- e! x5 r: h-Knowledge in ASIC/FPGA design process and verification tools.
7 T: q$ [; B; I-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
7 ?$ i' A" ^$ \- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
  s- w, X' C! o- K. h* I2 L  Y-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer

, _7 o3 C, d2 Y2 ?$ P9 P公      司：A famous IC company
# o0 m! o* C7 M" z工作地点：上海

Duties
6 N  G4 u2 Y0 T8 o* {Work with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
5 q: s; n$ ~+ }- k3 ~Work out critical design flows and methodologies to execute implementation flawlessly.
Design and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
Help and mentor junior engineers.

9 b8 F# _7 Q% b* J: \. vJob Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
3 S- f# W' l( x/ ZHands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
. A4 Y! t1 n$ B3 l% EExperience with ARM platform is preferred.
0 _! ^4 ?3 p2 E( SExperience with low power design flow is preferred.
Experience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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