FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
招聘岗位：系统产品经理
5 ]$ r! ^4 }! w; r6 A  k$ s工作地点：Beijing
1 n$ M' P# ^3 S, K; o9 E) ^  N* ]/ |
, `( Y. W! ^3 w' N岗位描述：
主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
, u; l- @/ j* j; u1 R+ o3 V
+ ]& T# m& Y8 e7 v" n" M" V$ j- s( L职位要求：
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
+ o  H' r- b  C; b  [招聘岗位：SoC System Verification Engineer
' s6 s; w& N+ r2 T工作地点：Xi'an

1 i: |/ D4 q( A8 Z8 `# T岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
) L1 D4 G8 b% S3 dJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
, j  I4 E) g* u# L工作地点：Beijing
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岗位描述：
& q  Z* ~& o5 UDuties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE

职位要求：
Requirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
招聘岗位：Sr. Design Engineer
  b( e5 B1 H; n& G  J) u' S工作地点：Shanghai、Beijing
+ x. g4 H' H# _0 g5 o; C; J
岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
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; d$ E0 `' C6 }, n. t; D* _( ~8 d, c职位要求：
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Product Engineer
' V# f0 P: y; A4 E7 T' R1 a; z工作地点：Beijing

岗位描述：
& C2 S" Q5 v1 q! Z# E+ ^( s- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system
+ x* d& Q* a/ z& q# v1 a/ r
职位要求：
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
地点 Shanghai
+ Z( ]# l9 j6 K1 Z0 S
职位描述
1 A( k& x$ V8 t+ m" s$ tWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
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职位要求
4 d7 b! N$ a$ C. tExperience in the following areas of expertise is desired:
3 S! N' l( g- n/ Q8 S4 |Wireless media access control (MAC) design experience would be highly desirable
& [! c3 P- m- f8 G! L/ mKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
4 z+ H) x5 n% s& k' N/ fRTL design, verification, and chip integration
Experience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)
* p' I5 O" T+ W0 X+ i% k- sKnowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup
8 n+ V  G& \& P
Other requirements:
* f: e1 r* z+ X; M6 ~Familiar with design and verification languages, EDA tools and ASIC/SOC design methodology
! O/ O( m9 `! {4 CGood script language skill, such as Perl, Tcl and Shell
; G% L. H6 }% `; }6 J  @5 q$ SGood written and oral communication skills in English
Good Team player
Candidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
% W6 m6 V' G/ ~; U- j& q招聘岗位：高级ASIC设计工程师
工作地点：Shanghai

# r  b2 q7 V2 q岗位描述：
) C9 x" a: P: R1 |/ H" t4 p1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。
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6 W0 P, P* ]% H; p" I# W$ C职位要求：
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer

公      司：A famous IC company
  u& t0 O! K- M' ^. ^2 ^; W" q工作地点：上海

) H! O5 R5 ?- o5 TThe Role:
·         ASIC  verification
·         Work closely with the California teams
·         Support chip tape out and bring up
% k6 L- j  {' ~) U" }
. Z' w' |5 C! x0 p* e- SRequirements:
·         3+ years experience in ASIC Verification
9 O, F1 h  I$ U/ I·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
# b/ o. u# D$ D2 z# \1 r) c8 V·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
1 k  {% d" I; V9 B·         Functional coverage and code coverage analysis
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
) L* `6 _' u4 {& P7 W8 b·         Working knowledge of C programming language
( Y+ }/ a2 @" n0 y·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
8 ^, S; [0 v/ {( o·         FPGA emulation experience a plus
. D6 ^1 D- ?1 |# E·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
  B/ q$ L6 ~4 G公      司：A mobile chipset semiconductor company
工作地点：上海

( R: w0 r; q8 Q5 m$ b- OResponsibilities:  
  g' k& }" y8 i* L7 S0 s  Make verification plan for one module or whole chip.  
, \( L: H1 W- N( E& O/ ~' J; N  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  

! x' G9 @: p3 x$ w: _* ^- [Qualifications:  
+ s3 i) \. a: Q! G1 z6 E' m& \  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
- Z7 I9 g9 ~' I* q6 q  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
2 Q* G& ]# v" V0 X+ Y; }  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
5 r" x2 m- K0 N% E. a# j8 {2 D  Good knowledge of software design is a plus.  
# E6 P8 F* u7 b6 b! U  g  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
工作地点：上海
# A1 D- u3 B3 y7 O2 o0 k
+ r0 c" Q1 V! M* Q& h% a8 Q6 QDesirable
Strong understanding of microprocessors
A good understanding of the interaction between software and hardware
+ k* Q9 s# D+ Z. c# r- y* UUnderstanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
$ V" I6 l6 U8 b9 u6 f# q- c: yC/C++, assembler coding or other programming skills.
Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred
1 e+ h) S: F) Q3 T# _' e
6 _* X4 k3 s' N1 X' ?5 V4 SJob Requirements：

tk02561

Education
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
' ~' c/ C& V8 J  x. g; O$ J  
Experience
& q( r5 {8 A$ O, @6 b$ ^% T$ ]+ gMinimum of 4 years industrial experience
Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
4 C' z, m" n, w! I# |) uExperience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
' i+ a1 L1 E1 N' E: xProfessional experience of customer and sales interaction
" M/ F" {- E6 D, Q0 u: uDemonstrable experience of problem solving and debug skills
6 Y3 v& J+ p" |
Personal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
& C! r5 x( E6 Z; ^. `Must be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
7 g4 f( d: Q4 t/ m! @1 oMust have the desire and ability to solve problems quickly
Must be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
- P; u6 V$ p* f) y0 M6 e$ ^Must be willing to be flexible and accept new challenges
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
; ^9 J7 ?! e9 b* ^6 p: }( @2 K公      司：A leading semiconductor company
工作地点：香港
; @2 h/ }7 ^# V+ p; q/ S" p
Job Responsibilities:
    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
) p. ?: j* h: O* [) }+ T; q; }" q+ H    Develop verification environment and coverage closure
8 E3 a2 Z1 ^* m. w  t8 o    Support wafer level testing and silicon evaluation
    Prepare technical documents
: D1 t" @! J% S, K& L6 R
Job Requirements:
& c  l2 O& a6 b. v2 \. s( h- s* [6 I    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
3 b8 v# v, I- j  ?) S    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
1 g: Y4 x( T' x% \  B  ]    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
( j. }$ w1 H& ]3 {/ b$ V/ v& z8 x    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
7 H1 x" I$ R9 c/ Q. v3 P1 }1 B6 T工作地点：上海

岗位职责：
1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
4 O. ^3 v5 _" C3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
' m- n/ L; M8 s8 L3 S
职位要求：
0 t4 ?7 c9 M) H! H6 C( [6 A( U3 u1、大学本科及以上学历，电子、通信、计算机或微电子专业；
4 E  y/ J" O  F' K  C. w2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
8 ?: q0 b4 V+ P. x8 E0 F3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
. _' k/ p, G9 G' }5 ]+ M: Q, d2 F3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
5 E: D) M1 Q5 s公      司：A famous IC company
工作地点：上海
. _; S' j8 j2 e. o
( q' d: p8 X0 G4 |岗位职责：
+ Y8 B2 Y2 L# D; v2 S! _1、负责整个团队验证平台的搭建、维护
! M/ U) G& R2 P8 r2、先进验证方法和验证平台的评估、导入
5 U( e( N5 d, J5 F3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
) C& r( ?2 G5 A6 d1 m7 w
: H6 M! A$ Q* s* m, a& N职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
/ r" D- ?% a# V' z; H: s) N2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
- ^+ L0 {2 v) M) ^, k1 m4 |5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
公      司：A famous European IC company
" Z9 J2 k) J; c3 t2 |+ O工作地点：上海
; z9 g% S' j% B3 Y! V
! k3 V6 E- d2 g/ lJob description  
2 `1 ?6 g! {7 u: w0 U- define system partitioning of s/c circuits and system  
1 t4 _* ]" u5 v; H' c# u$ f8 k3 B- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
( \' S5 }7 ]  Z/ f% y- G- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

  Z/ i' ^, U/ G( t. D* ~) [Required knowledge competencies and attributes  
- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
- > 5ys experience in digital design  
) f- y' W* E: C2 |- l+ w- good understanding of ASIC mixed signal flow (Cadence based)  
- strong background in HDL coding, verification and toplevel integration  
% P, J' J! r, a; f& W3 V- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
- experience in FPGA development  
) r: h% ^! G6 F: W' j" p/ t- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
公      司：A famous IC company
工作地点：上海
$ `8 K. l6 Z0 H( Q
岗位职责：
1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
: e5 w( p7 }8 }2 n) W7 N2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
1 ^0 v; j& o5 v$ U8 d, E1 i1 |- k/ n$ p公      司：A famous IC company
工作地点：上海
  X: G7 X1 D/ H5 f
The Role:
& F; x8 i+ t( K0 t' _7 z        ASIC design and verification
        Work closely with the California teams
        Support chip tape out and bring up
; J$ K; Y9 Y5 U  A5 |4 \5 T
Requirement:
$ B- G$ D. n( p% I. H- [        8-10 yrs. experience  
% O1 c: C+ x( C& G3 R        Knowledge of Verilog / System Verilog & Perl
        Has worked on complex project; experience with 802.11 is preferable
" K5 S  V! p% s2 y* p        Can work independently - want him to take over MVE
5 j6 h/ U7 u. g4 _  m        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海
# [( m, E: O% v" L& q
Responsibilities:  
& a3 m$ O; Y6 Z- z  Make verification plan for one module or whole chip.  
' W+ O2 ]" g( p  Build up and maintain module-level and chip-level verification environment  
# X. m& d0 G$ x% C5 W5 H  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
: o! o9 q' ^  Z% q
: Y+ R% m% e' _0 k, ?( EQualifications:  
  Proficiency in logic verification.  
: T; g) a2 Y% q" e6 ?  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
' M) }7 {, I+ c  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  u2 Z/ f6 t) Y  L/ ?) y5 ~  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
4 b* i9 G% |; ~1 ^7 f7 p9 ^  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
公      司：one famous IC company
. X% c7 R5 x( _# u+ j工作地点：上海
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! ~( L/ q# b( V2 s/ U: Q. ZQualifications
MS in EE/CS/ME.  
( r! M& Z+ n4 RMinimum of five  years experience.
& _8 z7 Y/ P8 O2 J& V( tAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
4 b  \2 W7 l/ `/ ~Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
0 J) m, j0 X6 t% c( Y: H" `- d" tCandidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
9 B0 N0 I1 q( ~8 M$ _1 oGood knowledge of Perl and shell programming would be an added advantage.  
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- J2 o8 s* Z, \1 R1 E) W0 xResponsibilities:
) w1 c; Q$ Q! C+ x+ p-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
# b: q5 c/ ]% D! j; e2 D1 J-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
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Requirements:
) c3 g8 a; o( U. I, wExperience & Skill: 5 Years
& }" a3 c3 [3 ^# o$ x-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
9 Z! A7 V6 b$ t/ }* E# \) k; b- Scripting and automation skills (tcl, perl, makefile etc) a plus.
& y9 \- [) m; M. R8 s-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.