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樓主: mister_liu

FPGA verification Engineer most difficult job functions?

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發表於 2012-1-6 14:38:45 | 顯示全部樓層
招聘公司:A fabless IC design company
  \! I2 T0 c6 s% U  a5 z招聘岗位:系统产品经理+ I, ?4 a5 `6 w9 K6 k
工作地点:Beijing
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( |* Q1 N% C9 X3 m% _岗位描述:. N9 y* F  u/ y- X9 m
主要职责: 定制芯片的实际应用方案,为客户提供具体系统应用的解决方案,统计芯片在应用中出现的问题并形成改进建议书。 ; j% C2 W) M0 _" ]& A1 a

8 d, {* H. W. b: h职位要求:
' w% Z8 R3 ?  W# {% J& o3 T职位需求: 1. 计算机、通信、电子工程类专业,本科及以上学历。英语CET-4级以上水平,良好的英文读写能力; 2.了解民用消费类产品的框架结构及应用领域; 3. 具备较强的芯片级理解能力,对高速视频接口(LVDS, DVI, HDMI, DP)、数字电视相关芯片有深入的研究或应用,可以很准确的知道芯片的指标含 义和解释; 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件,熟知原理图设计,PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件; 5. 具备敏锐和快速的反应能力;良好的思维能力、信息收集、分析能力; 6. 良好的团队合作意识和沟通能力; 7. 适应经常出差,勤奋刻苦,爱岗敬业; 8. 具有较强的嵌入式软件编程能力,熟悉LINUX系统的应用。能够独立调试系统系统软件; 9. 具有产品应用及管理经历者优先。
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發表於 2012-1-17 09:49:56 | 顯示全部樓層
招聘公司:A famous IC company
6 Q) o' \5 O+ x  n, \招聘岗位:SoC System Verification Engineer) e( }: [9 F$ q' I% P
工作地点:Xi'an& n3 ~5 C, \  |. _# G% \0 k

4 f7 P/ \' v4 N岗位描述:
+ U; A" u% K. F% q9 RJob Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team
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發表於 2012-1-17 09:50:02 | 顯示全部樓層
职位要求:
1 ^- D/ M* v7 `+ p' V3 a. X1 G7 `0 `Job Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented
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發表於 2012-2-20 13:48:28 | 顯示全部樓層
招聘公司:A famous IC company
. O9 w5 k0 ]( b招聘岗位:Digital Design Engineer* B+ S9 e& M& Y2 R# h7 i" a
工作地点:Beijing& C- c+ `, a4 l3 F3 V9 f6 N" s

7 t: W4 x' \0 H* U  F7 Q岗位描述:) J# R9 I# |2 z# J& B& s
Duties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE  i  U  `9 S# q' p
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职位要求:, @- i% c: d4 K# r
Requirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills
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發表於 2012-2-20 13:49:42 | 顯示全部樓層
招聘公司:A famous IC company
- y0 r- L3 b# U1 I招聘岗位:Sr. Design Engineer
/ {/ \: i: }$ p8 h# V& y( g工作地点:Shanghai、Beijing( k5 m6 u, d# r/ ]: J) w  U

$ M) ?8 a2 U- h7 Y% [) [1 C/ u5 I岗位描述:
+ ]" l, g* O0 X7 ~9 zDuties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow/ v% {$ N5 x, e" m. p0 }7 _# d
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职位要求:2 @+ i2 C3 u) T8 j! p
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills
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發表於 2012-3-19 15:10:21 | 顯示全部樓層
招聘公司:a top 15 semiconductor company# z1 W$ s* H, @5 @! X/ g
招聘岗位:Product Engineer# _+ M( ?- j8 j: N# @
工作地点:Beijing
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7 r4 _2 Y9 Z/ ]1 A: F+ d% ]  O# o岗位描述:5 b( N" ^" S2 a/ C7 d
- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system7 f: ?2 a8 g! n% _) s
8 @) J  a- O5 v1 v( w3 w
职位要求:
" x; N$ R6 r0 Z! G- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills
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發表於 2012-4-12 10:21:28 | 顯示全部樓層

Staff Engineer for Digital MAC Design

客户 A famous IC company( @8 v4 l$ l- \1 ^( I+ v9 ^
地点 Shanghai
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/ V. U' h: l) z  T职位描述* e/ f/ q8 `, s4 c5 n8 Y. W; K
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.$ l  q' K( q4 }# A" h
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职位要求; o" z  a- N4 Q
Experience in the following areas of expertise is desired:
$ v9 L0 s! j9 M6 X0 `; P4 zWireless media access control (MAC) design experience would be highly desirable/ E( U. c  V' G/ j% H' s# ?6 o! U
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus# d& o7 M1 i+ {: z/ @' i- s5 [
RTL design, verification, and chip integration ; M  C' a$ o: O$ `
Experience in the following is beneficial but not necessary requirement:4 K" g+ D3 Z% t. d
Communication systems and RF systems
- s+ c- {6 I* _+ s/ ?Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)! l4 T( T2 M" Q) ], P: n
Knowledge of interface protocols such as PCI/PCIe would be a plus
9 v3 [% |/ W; _) C; {7 c! oFPGA design flow, testing, and emulation bringup
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- I# s: I/ Z$ u# G' O: t! c9 B$ N; VOther requirements:
5 F4 |5 V, v( L; J; AFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology( x$ h6 u! P8 {$ C$ @: y3 u
Good script language skill, such as Perl, Tcl and Shell
% o4 {9 c1 n- l4 g6 g, XGood written and oral communication skills in English
$ k( m% ~5 G- j( ~; i' W( U; sGood Team player; V; k& r0 U. R6 `; ^5 a! q, V
Candidates must have MSEE degree with at least 5 years of experience
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發表於 2012-4-18 17:28:58 | 顯示全部樓層

高级ASIC设计工程师

招聘公司:A famous IC company
/ Z* W8 p9 l- b# X* E( V招聘岗位:高级ASIC设计工程师" k9 E8 O6 @2 @2 H% C
工作地点:Shanghai; }8 i  d6 q/ D$ L
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岗位描述:
# ?- |* L0 L' E1、定义设计模块结构并编写芯片设计规范; 2、使用VHDL/Verilog编写逻辑模块的RTL代码; 3、编写测试向量对模块进行仿真验证; 4、在FPGA平台上进行芯片级的测试验证; 5、进行模块级的芯片综合与时序分析; 6、编写完整的设计和验证报告。 , z# M' L/ A7 c' N; c2 a% A
$ w* _! W' S+ D+ ^
职位要求:
. h& X; H5 M+ K# e1、具有电子或通信工程类硕士以上学历; 2、 熟练运用Verilog/VHDL进行芯片前端设计,熟练运用设计仿真综合和测试工具,如quartus,Xilinx,modelsim,nc,debussy,逻辑分析仪,信道仿真设备等; 3、深刻理解数字电路设计和时序分析方法,并拥有故障定位和解决问题的能力; 4、深刻理解通信原理、数字信号处理等基础知识,熟悉无线通信原理与常用算法; 5、具有3年以上芯片设计经验,拥有无线通信物理层开发项目(如DTMB、CMMB、DVB、3G, LTE等)经验者优先; 6、工作认真严谨,积极上进; 7、良好的团队合作意识和沟通能力。
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發表於 2013-10-30 14:16:41 | 顯示全部樓層
Verification Engineer7 b' |) L7 K7 H5 F5 v6 |; K
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公      司:A famous IC company
" y' Z+ Y+ W$ K# y; ]工作地点:上海1 G/ G' _; m' ?

# Y3 I4 n3 ^, v; f" dThe Role: + o' @5 y- q( s6 c
·         ASIC  verification 9 c+ L! a9 m1 f( b, ^
·         Work closely with the California teams 8 E# q# y$ f! T* P
·         Support chip tape out and bring up : N8 k  k* O8 u1 e9 I  K# ]/ S. H
; U" X/ f7 L& ~0 \, A$ ?
Requirements:
1 n" F( i& I* Y2 w; T: f·         3+ years experience in ASIC Verification - B. u' k- E) z7 ?" O( t
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
4 X  @0 b) E; |2 p6 {  @/ T·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
( g* t/ y, s6 h. c) @3 m. [·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
* ]- e6 G: Y) \; ]% }/ {! r·         Test plan and test case documentation + ^5 E1 W) ~  Z. d6 v
·         Functional coverage and code coverage analysis 8 i) e: d2 G7 F) i: z
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc. + b, N( x- k/ ?
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB , p: v" ~1 b1 K& ^! V
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
/ K' J, Y6 b6 `3 a3 `$ @8 U·         Working knowledge of C programming language
+ c" ]; L' v2 Q5 t: r' y, d- t) H·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off 6 d9 {1 X! l4 ^) A+ e& \
·         FPGA emulation experience a plus
! X# x" K+ ?  M, ^" U1 f* P·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
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發表於 2013-11-13 14:39:35 | 顯示全部樓層
ASIC Digital Verification Engineer  S* \) g2 D. r1 A' T* A
公      司:A mobile chipset semiconductor company, s3 S9 `& E8 p* R
工作地点:上海
2 j8 z' Y: }% ?/ S9 ~& O6 ^4 I$ p6 f$ e$ E/ q- o9 Q( C
Responsibilities:  ' t$ X1 `% L( s
  Make verification plan for one module or whole chip.  + b: M6 B8 z! q" ^6 s# K7 z2 ]
  Build up and maintain module-level and chip-level verification environment  + T# L" z6 K# s1 x: ?4 i
  Verify ASIC digital design based on case list, and output verification report.  ( j0 W( y: M) {; m
  Also responsible for lint checking and formal verification.  # {. r- V- [6 }. r* p( \& ^
3 T9 a. w. A. H) |  j2 e9 [! N2 O
Qualifications:  
  ^5 h8 D/ P# _9 N1 F3 U  Proficiency in logic verification.  + J9 G& C& u8 K
  Experience with Verilog logic design language.  
& N6 r0 k+ h7 I( ?  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
7 y9 G8 H8 X* F+ w5 ^  Experience with UNIX/Linux simulation tools such as IUS or VCS.  " _( ?% \$ v+ ?* K9 n" \# Z
  Experience with C and C++ is a plus.  $ [. G2 s7 X1 G; w  `) `
  Experience with C_SHELL, TCL or PERL is a plus.  1 Y9 B9 O. M! M0 Z# J5 d8 L3 x
  Experience with UVM, OVM or VMM is a plus.  8 z: j* {* v0 ^8 p0 q
  Good knowledge of SOC design is a plus.  
3 @. q. e) Q" m6 `  Good knowledge of software design is a plus.  
( @, ^5 u/ j! ?9 J$ N" ?  Self-motivated and good team player.  ! Q+ ]; f4 E& M0 @" ]; Q2 s1 y
  MSEE or BSEE with 2+ years.
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發表於 2014-1-16 10:26:37 | 顯示全部樓層
Hardware Applications Engineer–Graphics: j/ F+ g- S* M" e; |0 i; C6 z
公      司:A famous IC company" V$ j* V; x$ x: k/ W* r" G- n: Z
工作地点:上海8 ?, _, _9 r9 z' R; G3 u9 T
( U, k* S9 Q. o, p! M$ Y
Desirable # d4 U' _2 q* x; f5 C6 J4 B
Strong understanding of microprocessors
; r8 Y4 X* d+ g$ T4 u! UA good understanding of the interaction between software and hardware , {+ P$ z' b( Y' M- R8 F
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout) 1 b6 D1 z) Z8 @. o
C/C++, assembler coding or other programming skills.
1 E/ H) |- y9 H- `Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred
6 `: H' y3 i1 @' m3 k4 c3 `1 O: l7 T2 ^4 i* ?' _. J
Job Requirements:
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發表於 2014-1-16 10:26:42 | 顯示全部樓層
Education ! z/ u' m4 F+ W+ o- K& o* p
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
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Experience 1 i$ z5 l( A( P; j2 ?: U7 ]
Minimum of 4 years industrial experience # g6 f2 J# ]# c1 e. R# @3 @2 s1 ?
Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL8 T6 ^# H( d$ v0 A" a- y! _
Experience in integrating SoC peripherals   x3 g8 S+ y" d
Experience of interacting with colleagues outside of China
: j- D" c+ ~; l) VProfessional experience of customer and sales interaction
5 R8 H- [# ]  a( |: HDemonstrable experience of problem solving and debug skills 0 |  [$ {; }4 ?$ X; ^* S% g

6 Z% T$ E( F! g; TPersonal Requirements
) n2 b+ b6 Y" a* M$ ?, f. @. _' T% cMust have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
8 I8 ^1 {% j$ o0 j% G$ W& lMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
' [4 @( r$ g1 P6 BMust have the desire and ability to solve problems quickly
  e( d8 I9 j& C  X, }5 x! Y8 i, {Must be enthusiastic and well driven ( F; h' L' V, u) n/ X  F
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
& c2 J: {* a; f" y1 [$ M: K) ]" }* J# EMust have good inter-personal skills, and be able to work well within a team; especially when under pressure 1 T7 h/ V3 x4 n6 ?' x( `4 T, O
Must be willing to be flexible and accept new challenges 3 G) O6 R$ d% @' \. c2 H5 \
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.
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發表於 2014-1-23 08:54:30 | 顯示全部樓層
Senior Digital Design Engineer# E( x) I1 o) U) z0 ~0 x
公      司:A leading semiconductor company! H7 x) M6 f! y( x
工作地点:香港
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0 R4 [0 ~! h" V4 Q3 tJob Responsibilities:
/ Q0 h* G' {8 a, ^. w    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis " D3 X# z; _0 a
    Develop verification environment and coverage closure ! m1 X: ^5 e. f( [! Y) L3 i4 O
    Support wafer level testing and silicon evaluation / }1 T* \# i9 v" x  x
    Prepare technical documents4 w, T4 z" v/ _1 `$ A" Q- h+ w# k$ J

, W$ b) |% ^' g: c* lJob Requirements: ' ]/ k0 ?6 A( \  D$ s3 i. c& i' Y
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
0 _& w5 ~1 {" R) B; _    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
1 T& i) ~  t; ~* s# y; l    Knowledge of SoC and embedded system. ) ~4 m/ |5 }5 d" q! M; o9 g
    Knowledge of scripting languages such as Perl, TCL and Make
- }, L; P- C! c0 R. L/ ]1 k  {0 M    Candidate with less experience will be considered as Digital Design Engineer
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發表於 2014-3-6 14:29:56 | 顯示全部樓層
数字IC验证工程师
7 `. S6 D% N* z  T公      司:A famous IC company
6 U3 |$ o1 u6 z工作地点:上海
( ]( ~6 V8 d/ w1 t" k
  _& T+ e6 ?4 b2 M" S岗位职责:
& v$ M6 B9 r) V4 n1、负责整个团队验证平台的搭建、维护
  g* j7 t2 [- Z: j- A& n. g' E5 A, W2、先进验证方法和验证平台的评估、导入 $ _: X; |; M! }. g4 E
3、各种IP的模块验证,SOC相关的集成验证、系统验证,负责验证计划的制定实施、测试用例的编写。
! V  _% e# w+ }+ T0 ]9 _; i1 V+ a% g+ d) T1 J' W& @# _+ @
职位要求: $ H0 `& [  L/ }
1、大学本科及以上学历,电子、通信、计算机或微电子专业;   T0 E. p' j+ z6 t: h& {, N
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程,有扎实的数字电路基础;
( m9 L$ g; K  l  j2 }# M3、熟悉SoC验证开发流程,了解常用的验证方法学,如VMM等;
& X2 _1 b! B) M$ F3、有1~2年芯片验证的相关工作经验; % M2 B5 V: ?' L$ J% g
4、具有较强的学习能力、沟通能力和良好的团队合作精神;
) x6 Z) t9 V$ o# }# J) G- z5、有基于ARM处理器的SOC芯片验证经验者优先考虑。
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發表於 2014-3-11 13:15:07 | 顯示全部樓層
数字IC验证工程师9 g" T5 k. \  m) U
公      司:A famous IC company; X( Q' j' ~# S" g" P
工作地点:上海
: d2 i0 g+ X! ?5 _# i# q4 m  G" d5 U! g
岗位职责: 5 u+ d7 u$ |8 p, ?0 W3 I% S
1、负责整个团队验证平台的搭建、维护
% @5 c. ^9 {+ I0 o2、先进验证方法和验证平台的评估、导入 / a1 S' M4 {) \3 y9 l7 Y
3、各种IP的模块验证,SOC相关的集成验证、系统验证,负责验证计划的制定实施、测试用例的编写。
2 v0 L! j! a. `: d7 W" o
  i$ g; o6 C+ O7 F2 l职位要求:   w0 i/ s  A# k5 P
1、大学本科及以上学历,电子、通信、计算机或微电子专业; 0 ?3 t. q- Q$ _- t5 v+ F
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程,有扎实的数字电路基础; 3 G) n; W. m1 t+ `3 j) ]9 B
3、熟悉SoC验证开发流程,了解常用的验证方法学,如VMM等;
0 s$ ~6 _. @* I& K# G+ ~# h3、有1~2年芯片验证的相关工作经验;
- O9 V8 N% a0 X$ e, Q4、具有较强的学习能力、沟通能力和良好的团队合作精神; * b8 {. V6 v2 |$ W
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。
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發表於 2014-3-28 13:07:37 | 顯示全部樓層
Senior Digital Design Engineer# d4 ^) X; w5 [5 b
公      司:A famous European IC company
. X- n0 G# R- M3 k. J3 D2 x工作地点:上海
& ?5 W8 @# P, C/ F$ u4 K  g( Q9 d3 m4 _# z$ W2 F6 J
Job description  
( b& U! c( ]7 q+ u) r1 r' \' C- define system partitioning of s/c circuits and system  % L' T# w& g2 I
- define HW/SW co-partitioning  ) p! m* R+ B! S" L0 ~
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  % ?$ K+ ?4 q. w
- propose new technical solutions on s/c and system level  
. b+ o4 h& U* e% S6 n. y- design digital part of mixed signal (smart power) ASICs  
9 [1 M- v# }/ n4 k* Y- u7 m) y- close cooperation and interaction with international teams  / H; M7 W, [+ }' H- U0 k! C
- coach junior engineers  
/ Q1 m/ g: f9 X" N3 H$ z# O0 X/ U/ v4 j* a& D) x7 B% |# W) Z
Required knowledge competencies and attributes  
$ d2 P9 T7 f, T& H  X1 a- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent) 6 o; H9 o  j- \4 q
- > 5ys experience in digital design  , J$ Q2 D" ?: k1 E' t# J, T% ?0 b
- good understanding of ASIC mixed signal flow (Cadence based)  ; P0 Z" R1 n# l. P. m; H' G
- strong background in HDL coding, verification and toplevel integration  
  K& o  W8 l' @$ z- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  8 D& E: n( g# P4 {, h: S  S8 o
- experience in FPGA development  
5 X: k$ z  S) O% d/ }  u8 X: H- very good communication skills (written, oral)  ' b- i  H4 u9 V$ G! t- b( a1 b* P
- self motivated and high level of flexibility  
* f! e, I( B- b8 z5 n0 r- foreign languages: English, German (not a must)
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發表於 2014-4-9 14:29:27 | 顯示全部樓層
数字IC验证工程师, x. l1 M! V3 I' t& M
公      司:A famous IC company4 z5 }* I6 A. j9 N
工作地点:上海
, ]* c! ^& x4 o3 a  `* X; I0 b
5 K1 R' ]( E4 D* t- L7 B岗位职责:
+ B: U4 |0 S" S0 K3 x. u9 n1、负责整个团队验证平台的搭建、维护
' s& _! {/ ~* m9 N/ s, B2 t( ^2、先进验证方法和验证平台的评估、导入
4 a  d( _- o- e/ W5 e' p3、各种IP的模块验证,SOC相关的集成验证、系统验证,负责验证计划的制定实施、测试用例的编写。
' A6 M! `& b% I0 D, ^/ J
) g* h0 }* Q. g' ~4 J9 u职位要求:
$ r2 G7 C. [1 X$ i; d1、大学本科及以上学历,电子、通信、计算机或微电子专业; ( G4 h3 ], J: }- l6 [
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程,有扎实的数字电路基础;   ]2 n/ D8 A; D1 x0 ?$ R
3、熟悉SoC验证开发流程,了解常用的验证方法学,如VMM等; 0 m& g& {% x7 J7 y4 {
3、有1~2年芯片验证的相关工作经验; ) B1 V6 g) ^5 f8 k5 A
4、具有较强的学习能力、沟通能力和良好的团队合作精神;
, y* Q1 S7 l8 _9 e8 d  u5、有基于ARM处理器的SOC芯片验证经验者优先考虑。
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發表於 2014-4-28 11:07:46 | 顯示全部樓層
ASIC Verification Engineer (WMAC)
/ F% k6 D5 E9 Z* z9 H" x5 i公      司:A famous IC company7 D! W  o8 H9 G1 w) f
工作地点:上海* g6 E  P( B# \. w+ n5 w- p
% \' W: w* A# ]: C' r1 b
The Role:
# H; _% L+ C0 q        ASIC design and verification 5 m4 A, p1 {% i
        Work closely with the California teams 4 K6 V: n- ^3 `* F1 q& G) S9 A
        Support chip tape out and bring up ; q9 h( F4 J) I& ]

- P9 G' s2 S8 x" ~. Y5 F" oRequirement:
" I" g8 r7 O2 X. Y" s% j) J        8-10 yrs. experience  
* j) ~$ X2 s/ W  T) s7 O        Knowledge of Verilog / System Verilog & Perl ( N' m& k2 z! U( t% g( F( B
        Has worked on complex project; experience with 802.11 is preferable 5 \- s+ q1 ]" ~( ~" H: r) Q5 U
        Can work independently - want him to take over MVE
/ ^2 |; D) F2 K/ o5 P# m        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus
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發表於 2014-5-14 14:02:31 | 顯示全部樓層
ASIC Digital Verification Engineer
/ f, w0 X9 ~# t4 t/ ?2 `. J( `" ]) B公      司:A mobile chipset semiconductor company/ ~  R& `  p. [; G; M9 Y+ x
工作地点:上海$ C! D' u0 a& i) J
% d6 M) c1 d7 w
Responsibilities:  / V7 ]& \( Z- e* J1 o. U  ~
  Make verification plan for one module or whole chip.  9 M# i1 B+ K+ V7 m. |
  Build up and maintain module-level and chip-level verification environment  % K, c0 F6 W+ N, Y, p" A
  Verify ASIC digital design based on case list, and output verification report.  
' a3 w- C+ w7 z1 r  Also responsible for lint checking and formal verification.  
2 A- Y* H% u6 I5 P$ C  r, X
( Q2 h2 V5 P9 J! T8 {Qualifications:  
* o1 K) q3 R/ B/ I; f  Proficiency in logic verification.  ! J& P7 U/ @* v5 o. S
  Experience with Verilog logic design language.  * m0 K; q) K+ S# p6 \! E9 v6 [$ ^
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  . ]9 s. l& k# t/ G. z9 L
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
6 A" `5 Z. i2 T% @  Experience with C and C++ is a plus.  
- S' |; k0 q2 |  Experience with C_SHELL, TCL or PERL is a plus.  
# y) m9 ]% {, W  Experience with UVM, OVM or VMM is a plus.  ' J. F' w) a  y% _2 [* G
  Good knowledge of SOC design is a plus.  8 M' k5 A9 E3 x" b+ j; p1 ]2 d5 Q  _
  Good knowledge of software design is a plus.  * P0 R5 `9 h$ @0 l
  Self-motivated and good team player.  
/ A6 D* c+ J/ O3 ?1 }- ?  MSEE or BSEE with 2+ years.
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發表於 2014-5-30 11:33:19 | 顯示全部樓層
Staff Verification Engineer
1 V' w5 P5 X% Q/ X' J. H: t公      司:one famous IC company" L$ A" R- r8 J- Q) i( X1 |7 Z. R) A
工作地点:上海
/ _, b+ f2 J4 q* n8 n, `$ ?/ j7 K4 O
Qualifications ( d' ]4 x0 |9 m7 y) O% j; W
MS in EE/CS/ME.  $ o, `0 R0 ~" e; \
Minimum of five  years experience. 0 A$ Y$ ~8 s8 R8 p
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.0 e3 C$ `  S0 H- I8 E8 W4 l
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
0 f) J9 m- T; \& v5 pCandidate should be familiar with industry standard ASIC design and verification tools and flow. ; n, [( K4 V( h% P. r3 e- Z
Good knowledge ddr protocol and computer system achitecture would be an added advantage. ) Y3 h# O. x6 f
Good knowledge of Perl and shell programming would be an added advantage.  
0 C4 S& t2 ~  ?+ b7 C  c; {( x
1 L) E/ u" ~; F: ^! B' XResponsibilities:
8 }" H' V6 }2 _( R  Q  H$ p: ?5 O/ Z7 J-Understanding the expected functionality of designs.
* w: I8 P& t- `" n0 B& d" K' T-Developing testing and regression plans. ; `  c! j1 \5 G( K
-Designing and developing verification environment. 2 J: T$ a5 q, B7 `/ w4 e) u
-Running RTL and gate-level simulations/regression.
6 z, j* M" t: j8 B0 o-Code/functional coverage development, analysis and closure.
1 J9 T# r* @: `2 f
6 M/ q. Y+ p- Y5 S2 Q* gRequirements: ; f" N1 w( h1 ]! [. C6 ?
Experience & Skill: 5 Years ; `5 \- }) G8 j' p* l, l! l
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
' Z( W' h1 J: P7 _8 Z) B-Knowledge in ASIC/FPGA design process and verification tools.
$ @% B/ K6 [+ N9 [0 k* K, z-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). : |' N) p2 v8 W* ?6 W
- Scripting and automation skills (tcl, perl, makefile etc) a plus. 4 I9 V( Z" I! o, G
-Familiar with C/C++. 6 T- b$ |' R- ^% x7 M5 `
-Knowledge of DDR protocol a plus. : Z3 |" I2 d- m
-Independent and self-managing.
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