FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer
* D- B$ C$ K1 x5 a" B
公      司：one famous IC company
工作地点：上海

Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
$ \' u; v. `' M3 _Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
& h7 ^. P% i4 I/ ~: k$ |Candidate should be familiar with industry standard ASIC design and verification tools and flow.
0 T$ P: T. E  w: F7 |Good knowledge ddr protocol and computer system achitecture would be an added advantage.
8 }$ U' [6 E$ w  G4 nGood knowledge of Perl and shell programming would be an added advantage.  

Responsibilities:
- x; h$ ^9 s$ `( P-Understanding the expected functionality of designs.
-Developing testing and regression plans.
/ m3 I. W# ]+ J( a/ s' W- W& o* \! }-Designing and developing verification environment.
) B4 O" T, u- [# P* Y* F-Running RTL and gate-level simulations/regression.
/ ^( y: v* ]9 e% ~% @& H-Code/functional coverage development, analysis and closure.

/ z% ]+ O0 F4 ^, v" |Requirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
. \8 }# s  N8 w4 u) v& r-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
, v/ i. X: A) T- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
2 W8 W' u2 m  u8 o$ F+ X' w
公      司：A famous IC company
- G/ {$ a- L) n1 ?% a工作地点：上海

Duties
) Y/ c! ]3 |- q7 H7 q9 @Work with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
, Q5 i, E) ]3 O& AWork out critical design flows and methodologies to execute implementation flawlessly.
. ?2 J7 H0 b) @" q% ^3 YDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
+ Y0 M" |2 C0 j2 d) V2 eHelp and mentor junior engineers.

Job Requirements:  
: a5 A# _" C- [% o' \Solid understanding of all SoC chip development stages is required.  
# f( A$ Q- i1 YHands-on Experience with complex SoC design flow is required.  
- ?& J# I- ?6 A: YHands-on Experience with RTL coding, simulation, verification is required.
/ U, x: g# O+ z! G6 h# B; oExperience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
( o7 p" p! h; m3 t3 _1 WExperience with low power design flow is preferred.
Experience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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