FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

公      司：one famous IC company
) Y5 ?! U8 K& \: P# g工作地点：上海

Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
# }4 H7 p! {: T. M# MAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
+ f) y6 Y9 o; l$ |" h1 v1 c' UCandidate should be familiar with industry standard ASIC design and verification tools and flow.
6 }3 C# ]1 O" R2 ]5 BGood knowledge ddr protocol and computer system achitecture would be an added advantage.
, ^( @# w2 _9 u# s" SGood knowledge of Perl and shell programming would be an added advantage.  

Responsibilities:
-Understanding the expected functionality of designs.
9 l* A: v, p+ }6 I+ U( l7 \-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

Requirements:
Experience & Skill: 5 Years
4 y3 i0 [, x! Q9 N% ?5 O2 w-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
. I# v* `; x6 }, F$ ?: R+ L-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
/ C3 m+ z- t6 b3 [# j
公      司：A famous IC company
工作地点：上海

. V# b, H9 e3 M1 }, W! UDuties
Work with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
4 O2 _* b% `3 l  s+ ?, Z+ RWork out critical design flows and methodologies to execute implementation flawlessly.
8 Z& H  `3 H# U6 d; X4 F; L6 ZDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
! }  K$ l, \7 ~9 dComplete full documentation.
Help and mentor junior engineers.
: V0 z$ A; ?1 ~& \" m4 j1 X8 ?) _
Job Requirements:  
( P4 C+ A7 Q* b% g/ g9 @& I! pSolid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
1 o; [) o: ~! i- E; ]; G4 BExperience with DFT and timing tools is preferred.
& T- [1 ?$ `+ }; s* J# xExperience with ARM platform is preferred.
( O8 Q$ V8 B' A/ X$ i; NExperience with low power design flow is preferred.
' @1 t2 L$ p1 m. eExperience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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