RF engineer's toghtest job function?

sophiew

Senior Analog Layout Engineer
公      司：a top 15 semiconductor company
工作地点：北京

6 p# S3 K+ s3 Y4 K, ~+ G& \Job responsibility:  
This position will participate in layout design team for analog and mixed signal circuits layout on CMOS and high voltage BCD process. Work through entire chip construction process, from preliminary floor-plan, detailed sub-block layout, and top level integration  and routing. Responsible for running full verification sequence using advanced EDA tools. The responsibilities will include but not limited to:
! a1 r" Y* f( H! R           Leading top level layout  floor-plan  and integration
            Transistor level sub-block layout based on schematics provide by designers, including careful analog considerations
+ Z: P5 U  k! @, G            Completion of DRC and LVS check and verification tools
$ Q0 s( l, F; {5 {- C            Hold and attend layout reviews
( O7 [- _9 z: R0 J
Qualification:  
            BSEE or above
            5+ years working experience as an analog layout design, 3+ years top-level tape out        experience
; d, |4 s+ H) M8 C& o+ h1 u            Experience of high speed circuit analog layout  
8 ~+ a( w8 o4 F9 A: h9 j3 }            Understand IC process basics
1 ^! d/ Z7 }) [  ]% \            Understand circuit basics and how they impact IC layout strategy
1 h! c5 c5 s* y) Q/ C            Good English language skill
            To be able to travel abroad frequently

sophiew

高速模拟集成电路设计工程师
公      司：A semiconductor company
工作地点：上海
$ e4 `+ K" s6 D  Y( ^+ H
$ c: d, K, I) V3 O, [职位描述：  
, I) G+ l" t2 g& k, Y! l1、负责高速模拟电路的设计、开发、优化；  
2、版图的设计及验证；  
% I# T; W$ U, h2 M0 w3、电路版图参数的提取及后仿真；  
4、芯片的测试和分析。

职位要求：
! Q/ s7 }2 Z" T$ V1）微电子、集成电路相关专业硕士或博士学位，或学士学位3年以上模拟IC设计经验；  
2）熟悉和掌握模拟集成电路及版图设计的原理与技巧；  
5 G5 Z1 R7 T7 s5 B. \) p: J3 {3）有通信系统用集成电路芯片设计和成功投片经验；  
! Y* D' y$ \! J, N4）善于沟通、工作踏实、责任心强，具有良好的团队协作精神；  
8 \% w% Q+ ~/ e( D5）有下述项目经验者优先：高速锁相环(PLL），时钟数据恢复电路(CDR），调制驱动电路，宽带放大器，限幅放大器，跨阻放大器等；