IP development & verification engineer/AM 請進來交流最難職位任職要求！

ranica

招聘公司：A Fabless IC design Company
招聘岗位：SenDigital IC Design Engineer
  {0 t" V" `( }6 i工作地点：Suzhou
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' {; B. \# D; u; h1 Y; p岗位描述：
7 H6 a! i( K3 Y, J, f- c职位描述： 1、参与芯片架构设计； 2、负责数字电路的模块和微结构的设计及RTL设计； 3、进行电路仿真，协助芯片的模块级和系统级验证； 4、芯片电路综合、时间收敛、面积优化、功耗分析、形式验证、板上调试等；
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职位要求：
任职要求： 1、通信，信号信息处理，微电子等电子相关专业博士或硕士三年以上工作经验； 2、1-2年CMOS数字逻辑电路设计经验； 3、熟悉数字集成电路前端和后端设计流程，熟悉Verilog等硬件电路设计语言； 4、熟悉数字逻辑电路设计的相应EDA工具 5、有商业芯片流片经验者优先； 6、要求良好的沟通能力和团队合作精神，工作积极主动，踏实好学。

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Digital Design Engineer
工作地点：Shanghai

岗位描述：
! i3 `* Y) p/ b# m2 P1 BKey Responsibilities: Preparation and review of functional and design specification for ASIC (ASIC/FPGA) Prove logical functionality and ASIC/FPGA code design/implementation. Coding of digital functionality form top-level down to block level Verification and simulation of needed functionality on block level Make test plan and test strategy. Ensure effective testing and high quality product delivery. Participate in system requirement and architecture review. Generating the test bench environment for the verification Responsible for test planning, test case definition.
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; |9 ^: h5 R+ o7 L职位要求：
Job Requirements: SoC development & Methodology Digital (ASIC/FPGA) design experience Very good Verilog knowhow and coding and modeling experience Complete understanding of the digital (ASIC/FPGA) design flow and process. Knowledge of Signal Processing, familiar with MatlabSystem Solid background in Digital Signal Processing/Mix signal design Good knowledge on Audio/Codec Good knowledge on IIR/FIR Filter design Good knowledge on sample rate convert (interpolation/decimation) Experience 3 year + experience in digital/mix signal design.

ranica

招聘公司：A famous IC company
招聘岗位：Customer Engagement Engineer (Graphics Software)
% t% _4 _- b' B3 g- n( s" }* W工作地点：Shanghai

岗位描述：
Background The Media Processing Division (MPD) within XX has the mission to be at the forefront of advanced multimedia IP products. The Mali range of Graphics Processors delivers an advanced architecture for hardware acceleration of graphics, tuned for low energy consumption and high performance. With considerable success to date and continuing strong customer interest we are expanding our customer support capability in the Asia Pacific region by creating a cross-functional team of software and hardware customer applications engineers. Customer Applications Engineer (Graphics Software) You will be required to gain a deep knowledge of XX’s GPU software driver products, build relationships with the relevant functional groups within XX worldwide and deploy this knowledge solving real problems in a timely manner for customers during crucial stages of their own product developments. The successful applicant will also aid in pre-sales technical support and, from time to time, will be expected to contribute to product engineering deliveries. The role involves a frequent amount of regional travel to customer sites, with onsite support duration ranging from one day to several weeks. An exceptional customer presence is essential, along with the ability to think and act remotely from central teams. Additionally, the successful applicant will be expected to spend some time each year updating their technical product knowledge at one of XX’s GPU software design centres in either Cambridge, UK; Trondheim, Norway; Lund, Sweden; Shanghai, China; or San Jose, USA.

ranica

职位要求：
Job Requirements Qualifications Good university degree in Computer Science or Electronics Engineering; Post Graduate degree preferred. Other engineering or science subject graduates would be considered if they have relevant experience. Experience • Kernel and Device Driver development and deployment, ideally for Android and Windows Mobile. • Development experience in windowing systems, for example X11. • Experience of customer and sales interaction – ideally in a Technical Support, Product Deployment or Field Application role - as well as development work. • Strong software design, coding and debug skills. • Knowledge of GPU and/or CPU architecture with an excellent understanding of the interaction between software and hardware. • Experience of working in a multi-time zone and distributed team environment. Desirable • Experience of embedded operating systems, device drivers, microprocessor and embedded system hardware architectures • Knowledge of Khronos multimedia standards and Microsoft standards • Experience in 2D/3D graphics technology and standards such as OpenGL, OpenGL ES, OpenVG, Direct3D Mobile, DirectX and EGL • Knowledge of Windows and UNIX development environments • Knowledge of the XX architecture, XX assembler • Knowledge of heterogeneous compute, ideally GPGPU/OpenCL. Personal Requirements • Must be able to travel on a regular basis, and potentially for extended periods • Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English. • Must thrive working in high-pressure customer environments, potentially alone. • Must be proactive in obtaining engineering or management input, either XX’s or the customer’s, in order to complete tasks in a timely and accurate manner. • Must have the desire and ability to solve problems quickly. • Must be enthusiastic and well driven. • Must be able to schedule own workload and plan tasks – based on both internal and customer requirements. • Must have good inter-personal skills, and be able to work well within a multinational team; especially when under pressure. • Must be willing to be flexible and accept new challenges.

ranica

招聘公司：a top 15 semiconductor company
/ F2 h5 T: S. N' `" @. @招聘岗位：Senior Digital Design Engineer
工作地点：Beijing

; u% h' [. ^; W. k4 |; X8 [$ z& q岗位描述：
: e$ ^, j2 v/ ~Responsibility: The responsibilities include but not limited to: 1. Digital micro-architecture front end design. 2. Develop RTL code for macro block and verification to guarantee functional correct. 3. Integrate RTL IPs into chip and run FPGA validation.
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" G4 P) s  E9 g  G# v# B2 @. A1 \职位要求：
Requirement: 1. 3+ years solid digital experience on design and verification area for MSEE/PHD or 4+ years for BSEE. 2. Familiar with scripts languages (tcl/perl/etc.) in unix/linux. 3. Good understanding on ARM processor or DDR2/DDR3 design and verification is preferred. 4. Experienced in System Verilog and advanced verification platform development (VMM/OVM/etc.) is preferred. 5. Good spoken and written English. 6. Self-motivation, result oriented, good team work and communication skills.

ranica

招聘公司：a top 15 semiconductor company
! n4 @! s+ h4 N1 o# g招聘岗位：Digital Design Engineer
工作地点：Beijing

/ t5 u7 l( z7 z; Y岗位描述：
Position description An opportunity exists for an experienced digital design engineer to work on the development of precision mix-signal products for industrial, Automotive and medical applications. The candidate is expected to contribute to signal chain understanding/partition, design and verification. He/she is also expected to solve complex design and verification problems requiring large scale analyses of probabilities.
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+ K- ^* w' a% k2 i4 E/ K/ N2 z- ~职位要求：
Qualifications Basic qualifications l MS in Electrical or electrical communication or equivalent qualification l Ideally 3+ years experience on RTL related design and verification l Good idea on sampling theory and digital signal processing l Experience with ARM type cores a plus l Experience with system-verilog, systemC or another high level verification language a plus l Basic analog understanding with real mixed signal ASIC experience is a good plus but not a must. l Strong teamwork abilities and strong inter-personal skills are required l Self motivated person with a strong desire to achieve result l Good problem-solving and trouble-shooting skills l Good spoken and written English

ranica

招聘公司：A famous IC company
招聘岗位：Staff Wireless Communication algorithm Engineer
工作地点：Shanghai

! c! o/ S9 ^5 h. W5 B8 {岗位描述：
We are looking for engineers to design, analyze, and implement advanced wireless signal processing algorithms. Algorithms to be developed, simulated, quantitatively assessed and refined. Participate in system architecture and testing.
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职位要求：
0 R5 A! h% b# G( v. Z' j& tRequired Skills: Experience in receiver signal processing design for the following: Wireless PAN, Wireless LAN, Wireless WAN, and/or cellular networks Modulation and demodulation Error correction coding and decoding Channel estimation and equalization Carrier and symbol timing recovery and tracking Filtering and interpolation Experience in the following as well is beneficial but not required: Knowledge of media access control (MAC) for wireless or wired networks Smart antenna techniques such as beam-forming, MRC, space-time coding RF system design and test VLSI design DSP algorithm in ASIC Candidates should be able to analyze algorithms in terms of circuit implementation complexity and power consumption. Candidates must have M.S in Electrical Engineering or related fields with some working experiences. A Ph.D. in Electrical Engineering or related fields is highly desired.

ranica

招聘公司：a start-up company with high performance bletooth and Wifi technology
) n( ?) p! D% x8 b6 L. G+ G招聘岗位：(Senior) System/Algorithm Engineer
, |! c7 v6 \" N0 o4 f工作地点：Shanghai

职位要求：
+ D5 n' @1 Z; n! O5 oRequirements: 1. Solid knowledge in communication science & technology, solid knowledge with modulation/demodulation related algorithms including GFSK, BPSK, pi/4DQPSK, 8PSK, QAM; channel decode; synchronization, timing recovery, equalization, etc. Solid knowledge of OFDM is preferred. 2. Familiar with calibration algorithms, such as AGC, AFC. 3. Proficient at matlab/simulink, can deliver fixed-point models to RTL designer, and guide the RTL implementation. RTL coding capability is preferred. 4. Debugging capability either in simulation environment or @ FPGA level & silicon level is a must. 5. Familiar with Agilent instruments such as Spectrum Analyzer/Vector Signal Analyzer, Vector Signal Generator, Logic Analyzer, etc... 6. Have more than 3 years working experience.

ranica

客户 Semiconductor China R&D Center
! f# n- v  E) b地点 Beijing

8 R- {$ h0 Q! E+ k& W* Z1 s职位描述
Be responsible for device driver development on xx mobile SoC products and BSP driver integration in Android, Linux and WinCE operation systems.
Be responsible for Multimedia, Graphic HW Engine Integration on xx mobile SoC products in Android, Linux and WinCE operation systems.
Be responsible for mobile solution system development including functionality development, stability and performance optimization. Mobile solution means the product such as smart phone, tablet PC, GPS navigator etc.
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职位要求
* BS, MS and Ph.D Degree on EE or Computer Science with over 10 years experience.
) @* H, m, H2 \- |3 `4 H" a: B1 b * Good C language programming skill with embedded C programming experience preferred.
/ _! Y3 R9 z% }0 k' s$ B* Good understanding of embedded H/W system based on MCU, DSP or MPU.
9 S1 r; J; b- O/ f4 A: N" C& o  u* Experience in SW development for ARM-based products on high-level OS(Linux,Android) will be a big plus.
* Assembly programming skill is nice-to-have, but not must.
! ]! C* d, H- _0 I+ |5 z* Experience with platform bring-up, multimedia subsystem, camera, 2D/3D graphics or connection peripherals is a plus
* Good written and spoken English ability.

ranica

招聘公司：A famous IC company
招聘岗位：Senior Build & Release Engineer
工作地点：Shanghai
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6 R* E" Z' M3 `3 M. T8 \5 c岗位描述：
$ e4 u) Z0 Z! U# nJob Description Introduction The Media Processing Division (MPD) in xx has the mission to be at the forefront of advanced multimedia IP products for the consumer, wireless and automotive infotainment markets. MPD is also xx's center for expertise in embedded software development. Key Responsibility We are currently looking forexperienced engineers who havediverse expertise in the software industry. You will be a key contributor in many domains, including but not limited to,further developing our continuous integration, test infrastructure, and build/release systems. As an early member to this group, you will help shape the culture and direction of the group as one of the key resource to xx.

ranica

职位要求：
6 i5 A7 T. p1 }7 y4 N' P2 r1 }Job Requirements Education & Qualifications Bachelors, Masters, or PhD (computer science or electronics engineering) with good academic records, or equivalent professional experience. Essential Skills & Experience

• 4+ years of professional experience in developing continuous integration (or build & release)systems
• Extensive software development experience with C/C++ or Java or C#
: V% J$ N& Z$ ?' T# f' H• Knowledge of Windows or Linux development environment, tools
( X- l0 D3 a$ r; T• Knowledge of software development process, Agile preferred
• Works well in a team environment
• Excellent learning skills Desirable Skills
. u* Y, ?. n6 K0 p• Knowledge of web-based product development and system integration
( }) b* X4 L5 p! v: t• Knowledge of version control (Git/SVN) and database management
1 J7 ]7 J* O! P; o  q' y" k( k( X • Experience in all phases of software development cycle
( d7 j9 E" J! g  P • Experience in working with open-source communities • Experience in the

ranica

招聘公司：A famous European IC company
招聘岗位：Sr. IC design engineer
, [1 g7 l" @" f6 y/ y8 [0 v工作地点：Shanghai
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" d- N& i+ |# N9 L' j岗位描述：
7 {, |; ~8 a1 X% y0 H* yRoles and Responsibilities - feasibility studies of circuits and systems (incl. HW design) - support product proposal and definition - analog IP and subsystem design and verification - top-/systemlevel verification - IC evaluation/debugging - test proposal and support transfer to production - plan and track project activities - coach junior engineers and interns

. g- u; E  ^/ M2 N& ]职位要求：
Qualification Requirement (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc) - master degree in microelectronic circuits or systems - > 5ys experience in Smart Power Design - good understanding of ASIC analog and mixed signal flow (Cadence based) incl. toplevel integration/verification - strong background in smart power s/c technologies - experience in DC/DC converter and DC motor driver/control design - hands-on experience in silicon evaluation and debugging - very good communication skills, team work and high degree of flexibility - foreign languages: English, German (not a must)

ranica

资深IC设计工程师(SOC方向)
% _$ P9 v- {- X" \3 ^( j2 m客户 A famous IC company
地点 Fuzhou

% M' Z; L( F7 n- j9 e7 A$ n& |职位描述
7 k& |3 t& y# N2 V, `" F具体工作及职责：
1、与市场、应用等一线部门进行充分的交流，参与IC设计项目的立项、Spec定义，并确定芯片SoC架构；
2、带领5~6人的团队完成SOC芯片项目的全流程研发、测试及量产；
3、对项目进度和质量负责，并能承担具体的技术任务；
4、组织具体技术难点的讨论和攻关；
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职位要求
$ [+ I. S( P5 e5 U* s3 b工作经历及技能要求
  ~( V5 n- G& z/ T5 ~; U1、有至少三年以上SOC系统设计的经验和至少一年以上的团队管理经验；
2、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程（从设计、验证到实现）；
3、熟练掌握应用处理器的SOC设计方法，完成多个项目的流片；
4、具有一定的领导力和执行力，能带领团队承担芯片项目，引导团队解决各种复杂问题；
5、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
6、熟悉芯片spec设计和SOC架构设计者优先考虑，尤其是基于ARM CPU的多媒体应用处理器；

ranica

资深IC设计工程师(图形图象方向)
) b- U! t9 o* T' Y; d  n% R客户 A famous IC company
地点 Fuzhou
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职位描述
8 o/ z$ B0 c& D0 c职位工作综述：图形图象处理和视频编解码方向

  W5 W. ?+ q  ~2 N1 I6 u( S具体工作及职责：
/ M; q5 N; P  R2 X! K1 R) v/ X" f1、根据市场需求和芯片定位，参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计、验证和交付；
0 T% J/ A8 j% s; m( p; B3 z2、对项目进度和质量负责，组织具体技术难点的讨论和攻关；
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) m! |6 j* T7 I2 `# `7 d' m+ b职位要求
工作经历及技能要求
( R3 O4 Y2 q+ P9 k; N! n有至少两年以上图形图像或视频编解码等领域的ASIC设计经验；
1、具备丰富的图形图像处理或视频编解码等相关领域的系统知识
) ^, ]* i& h& r! M2、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程；
3、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
: d" @. d+ Z2 f" z: a' C! ~4、有团队管理经验者优先考虑；
, N6 }) ~/ `1 \! m6 D显示接口(LCDC)，图形处理，图像后处理，视频编解码

innoing123

数字芯片设计工程师（DFT/综合）

- w+ e8 J9 Q& |' F1 |  t4 l" Z公      司：A mobile chipset semiconductor company
工作地点：上海

1 ?$ k# Q' z& }# u职位描述：
( _, x1 U2 N$ [+ Y- E4 E1、To provide and support SYN&DFT work for several projects in parallel  
2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation  
: [1 u9 Z4 @2 U: N4、co-work with designer and provide block level SDC file
5、co-work with Back-end team for timing signoff

5 G7 o- ?) S5 B$ |& {4 X职位需求：
1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
8 o* t1 l* D0 ?3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

ranica

资深数字IC设计工程师（SOC方向）
公      司：A famous IC company
& b5 d' K8 z/ ^/ Y工作地点：上海
! y/ _+ B" S' Y3 H6 `* Z
岗位职责：
5 E+ j4 q; ~& {  o$ t+ {% E1、与市场、应用等一线部门进行充分的交流，参与IC设计项目的立项、Spec定义，并确定芯片SoC架构；
2、带领5~6人的团队完成SOC芯片项目的全流程研发、测试及量产；
2 ~6 r; T& E  `0 A+ ?3、对项目进度和质量负责，并能承担具体的技术任务；
0 F3 ?& T* O; q. z& F4、组织具体技术难点或紧急任务的讨论和攻关；
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岗位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
$ t& [0 u  n* ~+ T2、有至少两年以上SOC系统设计的经验和至少一年以上的团队管理经验；
3、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程（从设计、验证到实现）；
& Z( L6 @3 o/ u2 }  I4、熟练掌握应用处理器的SOC设计方法，已经完成多个项目的流片；
9 b3 V0 A5 J- \% ~5、具有一定的领导力和执行力，能带领团队承担芯片项目，引导团队解决各种复杂问题；
6 @1 v  b! e+ K) u- W; ]7 `! c6、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
7、熟悉芯片spec设计和SOC架构设计者优先考虑，尤其是基于ARM CPU的多媒体应用处理器；

ranica

ASIC Verification Engineer (WMAC)
8 ~- q% J: D' T6 }) i
公      司：A famous IC company
7 Y7 ^' Z2 O; H2 u" D工作地点：上海

The Role:
0 d' n) b3 T7 z$ j" Y8 p        ASIC design and verification
        Work closely with the California teams
3 D# F+ `% {; h8 y4 r        Support chip tape out and bring up

- e$ U0 ]) v) Q) yRequirement:
        8-10 yrs. experience  
& p3 }; W# ?# U3 @        Knowledge of Verilog / System Verilog & Perl
2 y) p  j) T+ o9 U0 |9 o        Has worked on complex project; experience with 802.11 is preferable
        Can work independently - want him to take over MVE
! {8 X+ G! k5 @% J4 O        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

Job Title igital verification Engineer
2 k* e  Z% ^5 Q& Q0 w% i5 lJob Category :Semiconductor
Post Date: 07/08/2013
- V9 E) J* ^. s# jLocation : Singapore
Job Type : Permanent
# P  z/ Y$ m: i% a- uJob Description:
$ v& ~& c  T- L9 H. n/ t$ G$ ELooking for SoC Verification Engineers Experienced in System Verilog Tools
1 _" \& P  \3 z- L% ^% F( ]Responsibilities:

# u8 \+ D- G% p2 ~& ~* T# p* aConstrained-Random Verification using SystemVerilog.
Develop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.
Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests
1 M: {$ P" K3 s4 r# ~: |0 TDeveloping and reviewing test plans
+ w  r8 v+ a4 X1 i' Y/ B9 uWrite coverage monitors to evaluate the coverage of the DUT.
Formal verification using SystemVerilog Assertion to verify SOC or IP is plus
5 j9 H6 r' s+ W4 f# B1 e4 t
Requirements:
0 ?" n6 X+ e9 E  n, y>4+ ethernet switch background
5 k1 L! p6 _5 M8 y$ H1 a1 fAt least 3-year+ experience on digital design and verification
: j6 o, p! h: S+ ^Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
Familiarity with transaction-level verification at higher-level of abstractions is plus.
. t4 h3 o0 ?6 `+ B( W6 \Experiences in developing measurable verification plan.
% Z) \& w( O- b4 \' YProficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.

ranica

芯片设计工程师
  o1 ~, O2 s  x6 A公      司：A chip design company
6 G* V6 @: w8 r: j; i% z1 y工作地点：深圳

岗位职责：
  n& ~% j* I) I8 w6 B1 C2 S1 a     1.芯片模块的设计与验证；  
     2.独立完成模块级结构设计，RTL实现以及相关验证工作；  
* ]& }# Z3 s% c2 }8 f     3.参与FPGA系统调试和验证；  
     4.参与芯片设计整个流程。

岗位要求：
% P% w7 ?& N. \. U4 [! i      1．大学及以上教育水平，电子类专业
4 ]) Y" q, I% C& D5 t& D; j      2．熟悉数字集成电路前端设计与流程
      3．有数字集成电路设计与验证经验
      4．团队合作精神