訊號處理及通訊系統設計技術焦點 ?

ranica

工艺工程师
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0 Y# V+ e. ^  M& e公      司：A famous IC company
工作地点：北京
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岗位职责  
1、执行公司已认定的制造工艺流程、工艺参数及产品标准；  
2、执行工艺流程、工艺参数及产品标准；  
3、优化工艺流程，解决生产现场存在的工艺、技术问题；  
4、检查各工序的工艺执行并做好记录，对现有生产技术进行必要的研究并提出改进建议；  
( ^$ w6 C; u7 ^4 p1 _; e; |5、负责完成产品的试产报告与工艺分析报告。  

任职资格  
1、微电子、半导体材料、材料物理与化学、等离子体方向本科及以上学历；  
2、3年以上工艺技术工作经验，熟悉光刻工艺、刻蚀工艺、MOCVD工艺者优先考虑；  
3、熟悉生产工艺、产品性能、产品结构，具有丰富的项目开展经验，团队意识强；  
4、能够阅读并解释、运用各类技术文件及说明，具备解决现场故障的能力，统计调查分析能力，善于发现、寻找并解决问题；  
9 M, v7 j+ H  H" {3 H5 L5、有责任心，能吃苦耐劳。

ranica

CIP Engineer

公      司：A major supplier of wafer fabrication equipment and services to the worldwide semiconductor industry
工作地点：上海
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Overall responsible:
Responsible for delivering CIP solutions and proactive productivity solutions.

8 e' q/ x6 C  d1 {Responsibilities and Scope:
9 t% D9 A, J, m7 B-Gathers, validates, analyzes, and communicates equipment performance for assigned installed base.
-Identifies and communicates revenue opportunities & product improvement opportunities.
-Closely work with Account Team and customer to ensure on time delivery of CIP and productivity results.
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Competencies:
-High level of system technical expertise.
, O2 k9 s$ C0 F4 `/ m5 c" `2 s7 ^/ z-Excellent analytical skills.
-Excellent technical presentation skills.
-Strong ability to influence in a cross-functional environment.
$ q4 @+ {- y% }, Z-Excellent understanding and ability to apply SEMI Standards to equipment performance data.

3 [3 Q% |" C" hRequirements:
-BS Degree (or higher).
  ]" \; X* o3 p1 m, m0 a-Minimum 7 years experience preferably on Lam equipment.
-Expert level process or service experience.
-Strong understanding of Semiconductor Fab Operation.

ranica

ield Service Engineer (Etch)
9 f- w/ u+ D: _' j/ d- m
公      司：A major supplier of wafer fabrication equipment and services to the worldwide semiconductor industry
工作地点：西安
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Responsibilities:  
# p5 ?/ h7 S, c- Z1 Y-Be responsible for quality machine installation and maintenance service of complex electro-mechanical systems.  
2 f2 ?+ F4 @! ?/ h0 G+ M" n( g-Analyze and troubleshoot technical problems.  
-Draft technical reports.  
-Extend interface with Lam customers and provide training to customers.  

Requirements:  
·Bachelor degree, majoring in Electronic Engineering, Mechanical Engineering, Semiconductor Engineer and etc.
* t: V  D$ ~+ T·More than 2 year relevant working experience.  
·Effective communication and interpersonal skills.  
0 G/ b' \% F9 g' ?& M! f! d! `9 \·Good team player, willing to assume hard work.  
) w/ @! ]0 E1 L·Fluency in writing and oral English.  
$ K$ c, b7 ]1 a# W' M·Overseas training will be provided.

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Device development engineer
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公      司：A famous IC company
工作地点：上海
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Duties
·         Facilitate product design work in foundry process(LG, MS and BCD process).   
·         Have a strong device/process background for 90nm~0.18um logic process, mixed-signal, embedded FLASH memory, and BCD process.
. n& P0 ]$ K6 D4 Y1 o, p3 x·         Tasks would include answering device  and process related questions, interpreting DRC and LVS results, helping with tapeout and mask ordering, doing jobview mask inspections, and also participate the process/device development projects.
2 w7 |4 M) `: A1 [" @9 r" V·         Would be expected to establish relationships with his technical peers at foundries and discuss important technical issues with them on an almost daily basis.  

" Q; M( K9 b9 s  l9 s* XRequirements
+ f, E. E  n8 b% B; Z·         Senior level engineer (minimum 8 years experience with BSEE or minimum 5 years experience with MSEE or PhD)
·         Excellent device knowledge (LV CMOS, BJT, BCD, embedded FLASH memory, OTP/MTP, latchup, ESD, device reliability)
·         Excellent to very good knowledge of PDK systems (design rule, verification software, mask ordering, device pcells, circuit modeling, parasitic parameter extraction, and so on)
' y( u& i0 P" z3 B2 @·         Some knowledge of circuit design, primarily from a device usage standpoint.  
·         Knowledge of major Asian foundry systems, process technologies, and devices would be a positive.  
·         Ability to understand and solved technical problems relating to semiconductor devices with a minimal amount of guidance.
9 V% a( Y2 O% ?; O! D2 e·         Excellent people/communication skills

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Sr Analog Designer

$ G- A' `4 X8 E3 t+ \4 z2 A公      司：A leader in high performance analog and mixed-signal IC design
工作地点：北京
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) O- ^+ v: M4 E7 O: e: ?3 Z5 ~职位要求
Education and experience requirement
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry
design experience
7 X6 `$ |5 a/ T      Hands-on CMOS product design experience in two or more of the following
areas
       Receiver front end, including analog front-end, demodulation, channel selection etc.
* f1 Q. }8 x' d/ w. e6 A3 C       High-precision ADC, including sigma-delta, pipeline etc
; Q2 q/ |; [1 c0 V       High-precision DAC
1 M0 I' K$ r; F7 d% ~% J/ L       Fully-differential continuous and discrete-time (e.g. switched capacitor)  amplifier/filter design
       High-precision oscillator/PLL/DLL
       Low noise voltage reference
: }+ A0 U: [  H! ^5 y       On-chip high-voltage charge pump
5 {# u6 F  f. o8 R" N  H3 \      Experience in system level definition, modeling and verification a plus
      Hands-on experience supervising layout and post-layout verification
" F$ |% H. n' E% X2 F$ K3 }. I      Proficiency in tools
       Cadence design environment
       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus

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高级研发项目经理
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公      司：A mobile chipset semiconductor company
* b: b' k( {/ K8 L9 ?工作地点：上海

( n% ~0 t) u4 T职位描述
+ L& o% O! X: F/ S  c+ o' o需求说明：全面负责公司产品的研发项目管理，包含前期产品定义、可行性分析，立项后芯片、硬件和软件研发，最终推广客户并实现交付客户满意产品解决方案。  
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招聘需求：  
1. 半导体、通信、计算机软件或电子类相关专业本科及以上毕业。
' z1 p* Z9 e. z! l2. 有5~8年的半导体、通信行业芯片或软硬件研发经验，1~3年项目管理经验。
3. 熟悉移动电话架构，特别是芯片和软件架构。
2 Z( X, D, M2 c0 [' P+ f/ [4. 了解移动电话开发生命周期，包括规划、研发以及市场推广。
5. 良好的沟通能力，特别是跨部门沟通能力，系统和结构化的思维方法。
- O7 Q. X9 w) f  V& E: _1 ?6. 具有较好的英文听、说、写能力。
$ X) }7 \3 }& ?- S3 @& \  H7. 有海外工作经验者优先。

ranica

LTE DSP RF驱动工程师

( p" z9 E2 v' [6 c6 l5 ?# R! Z. H公      司：A mobile chipset semiconductor company
工作地点：上海

, t- |+ J0 C  v$ k; Q2 B职位描述
1 通信工程/电子工程等相关专业硕士以上学历,3年以上相关工作经验  
* X# c. `' O7 S- p8 v2 熟悉无线相关RF（如：MAXIM射频芯片）调试流程,熟悉LTE射频经验优先.  
3 有半导体及芯片公司基带+射频模块调试经验者优先.  
4 熟练使用仪器仪表（示波器/逻辑分析仪/频谱仪等）调试硬件问题  
5 熟悉C语言，具有基于DSP的C编程与调试经验；  
6 对工作有激情，勤奋、踏实；可以很好的进行团队合作；

ranica

Principal/Senior Engineer of Analog PHY or SerDes IC Design
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公      司：Semiconductor China R&D Center
  m& u' Z* L) w* o; Y工作地点：上海

! V1 B1 Z. q2 nJob Description:
4 \- V( d) B7 G# D( K3 M+ |
6 }$ Z% I  A1 Y8 `1 m1 F" [# a1.Responsible for the design and development of PHY or SerDes analog/mixed signal IC circuit blocks from initial concept and specification through final verification and conformance to customer requirements.

  A2 q  A7 r% b0 n" Z2.Candidate’s background should demonstrate good problem solving skills, excellent analog aptitude, good communication skills, and ability to work cooperatively in a team environment.  
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2 ]/ [% n1 L. U7 X. G1 _/ o3.Must have demonstrated experience in analog PHY or SerDes transceiver designs including some of the following circuit blocks: System level modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; Voltage Regulators.

+ Y! G9 {8 S) w0 ~' s1 `4.Candidate should have working knowledge of a set of common SerDes standards and their electrical requirements, and a thorough understanding of jitter.
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5.Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and experience at 40nm and below technologies are a plus).

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Position Requirements:  

⒀ Master qualifed industry experience for at least 10 years & performed core role in this field.

+ @9 Y3 X$ _. k& b7 n% S, I1.Master or PHD (prefer) degree, major in Micro-Electronics, Electronic Engineering or equivalent

2.Ability to work effectively alone or as well as in a team.
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, Y: L. k: b% F1 h5 p4 W3.Essential that the individual demonstrates strong communication, verbal and written
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2 t0 A& l% ]/ z. W( ]9 ]& w; u4.Requires good communication skills in English.

5.Industry Experience for at least 8 years or more for analogy PHY or SerDes and High Speed silicon mass products

Desirable Qualifications:

# u' s+ |) I/ `) `0 v) I⒀ Analog PHY means both SerDes(for connecting one-connect) & HDMI PHY, DP (Display port) PHY solutions.

1.Knowledge of one of key SerDes Analog IC design areas and their architectures/applications:

2.Clock Data Recovery; PLL''s; Oscillators; Low Noise Design; RF IC building blocks

3.Solid understanding of IC design technology and process/methodology in IC design solutions

# }+ v5 X6 M/ j: |/ A4.Familiar with Cadence analog and mixed-signal EDA tools is a plus

ranica

代理商管理工程师

: }) t2 \0 q# m7 N0 Z% a公      司：IC设计公司
工作地点：深圳

/ m- E$ [: T# G. R8 p+ A工作职责：
1、        协助组织每月代理商采购、销售、库存等信息的收集、审核、统计、分析工作；  
1 Q1 T2 B' _" b5 W; S2、        协助开展和推进代理商开发、续约及终止工作，并负责代理协议的评审；
- V* m7 h: {. K4 C3、        制定和协助制定代理商发展规划、年度评估与评级、激励与考核管理；
4、        代理商和公司业务出货事务处理；
: }& Y& p, R* [5、        代理商出货数据监控及核查；
6、        公司进口报关工作的受理；
7、        协助推进和协调配合其他代理商管理的相关工作

! H% R1 E, s% X; {9 I* K/ g& i) P6 w3 w岗位要求：
6 i: C) k1 q+ p3 T8 @1、良好的数据处理分析能力、文案编写处理能力及整合资源能力；  
7 W1 e3 T' l- G, a2、具有丰富的渠道开拓与维护的工作经验和商务沟通、谈判经验，具有至少三年以上电子行业代理商渠道管理经验；  
3、良好的气质形象，理解力、沟通表达能力、组织与协调能力，较强的情绪调控能力；  
2 G) S  k. f# c5 K2 _+ _& _4、有强烈的事业心、进取心和责任感，有清晰的职业发展规划；  
4 t. J, b( J. y( |) g" X# j$ k5、工作主动性强，诚实可信，执行力强，思路清晰，善于解决问题，讲究策略，对临时性的突增任务有很强的承受能力和包容度；
5 L0 w+ Q4 ^  E- L6、熟悉使用EXCEL、WORD、PPT办公软件；

ranica

Field Quality Engineer, Asia
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" e+ R, o  h6 X$ L4 ?; y' w( l' S公      司：a world leader in graphite material science
工作地点：深圳

) F9 |! S6 {6 ?7 n, T7 jPrimary Function:
Carries out Quality functions for AET customers of finished parts, contract manufacturing as well as converters in Asia.
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+ G4 L+ j/ }+ ^/ M$ BDescription of Responsibilities:
Under guidance of AET QA director:
?Supports sales of finished parts at End Use Customer抯:
o        Helps turn customer抯 explicit specification and implicit expectations into inspection specifications.
o        Addresses customer抯 complaints and dissatisfaction in a timely manner, including at the customer抯 site as required.
o Runs investigations using specific problem solving methodology and manages communication to customers on these investigation and corrective action plans.
Is responsible for verifying final inspection results of finished parts at our Contract manufacturers (CM):
" }. p4 n" }$ D# Mo Helps ensure Customer specifications have been consistently implemented and updated in CM documentation system
o        Audits CM final inspection procedures and results
- m: s+ _3 a! y8 T# S: h9 No        Provides our verification of CM inspection results for prototype, pre-production and production stages.
o        Monitor抯 CM抯 Outgoing Quality control records, analyzes yields, identifies improvement opportunities.
" K. f4 s4 }2 S! h9 ^o        Drives Customers?complaint investigation at the CM抯.
7 J( P/ e) v0 U6 i?Supports sales of semi-finished products  at converters
o        Helps identify true end customer抯 needs as well as converter抯 needs and develop specifications.
o        Helps optimize specifications for semi-finished products so as to optimize the whole supply chain.
  }  F2 O: V9 u: }0 y) Bo        Addresses converter抯 complaints and runs investigations using specific problem solving methodology.

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Works in close relationship with: Integrated Solution process engineers, Lakewood (USA) plant Quality manager/engineers, Regional Sales Managers and Application Engineers.
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Competencies:
Customer focus
( E7 X! K6 x* d/ _Problem Solving
Sense of urgency/priorities/ Responsiveness
Attention to details
9 A( Z" j+ r: e8 p) A/ jFunctional/Technical Skills  
Flexibility
- W+ O6 e0 k( F3 v& E8 AIntegrity and trust

Knowledge / Skills / Experience:
5 years Engineering degree (mechanical degree)
) X5 q* n" D2 Z8 f/ o7 J9 eMandarin as mother language. Fluent English (written, spoken) is a must. Korean is a plus.
Good background in Quality system (ISO9000), Experience in Lean 6Sigma is a plus.
) e3 A# [8 [% O& j  y" `5 r% F8 v5 nMasters Quality tools as problem solving, standard work, and statistical analysis.
Ability to use Solid works is a plus.
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Working Conditions:
Significant travel. 75+% of time. Mainly in China. May include travelling to the USA, Korea and other countries in Asia.
Office and manufacturing (die cutting, lamination,..) environment at our customers/CM.