RFIC工程師門檻？要當RFIC Designer的三大條件？

tk02561

RFIC工程師跟RF工程師的薪水好像差了不少？

& o) n: h, M4 d! H8 M以上都只是入門的門票而已？

6 m9 G- r6 q4 j  `2 n; @哪項對你目前而言，殺最大？

ranica

Staff Engineer-RF

# ~+ @0 s9 V$ B! z2 Y4 D公      司：A famous IC company
- ]3 `: C5 L/ |% I3 L4 i+ P) k& n工作地点：上海
6 m. E! N% [5 e3 ^( V( m
Job Description:
" f, M0 V7 Z6 D/ A1 o# QRole as RF Power project manager for Shanghai Development Center ( SDC )
' U- n6 P0 i# b7 M- AMay be considered as team lead if relevant team leadership experience are evident.
Involved in installing and enforcing design rules, flow and milestones checks for SDC.
; ^6 F2 Q2 p2 p! T% }/ ~' cAble to provide technical guidances in RF Power modules designs( for example, RF Power module designs in the range of 400Mhz -2700Mhz)  and Doherthy designs.
Driver for technical customer interface for Design In and Post Design Win activities.
9 T8 I) d- D9 n9 l. ^Proactive in ensuring successful project execution ( cost, schedule and efforts )
5 Z7 @2 b8 a1 U2 o- ~Provide report to management of project and customer technical issues status .
Manage project issues with proactive tracking of issues and defining effective countermeasures.
Will required Hands On in PCB and System circuit design together with the junior team.
8 [' s1 n1 ~7 N& \/ G5 }Involved in Product definition of new RF Power module designs.

ranica

Qualification :
* j& l/ `  h/ x- ], b0 \7 E1 WBachelors/Master/PhD Degree in Electronic Engineering ( specializing in Electromagnetic Fields ,  Microwave & in RF Power )

Experience:
7 E. e9 ^; u, `8 g: h$ P+ Y' n# cAt least 10 years of experience in RF Power circuit design and application/system development.
Experienced in RF power amplifier designs , Doherthy amplifiers designs and RF POwer systems development.
Experienced as project manager managing projects in RF power designs with multisite overseas development teams.
+ K' k* f( c0 B' o/ ^+ j7 ?Able to translate customer requirements to specifications and to designing final products/systems according to the customer needs.
$ y# y, `$ x) G* }/ ?# ^0 c/ \Diligent in following company design rules, verifications and milestones checks for all phases of development.
Familiar and experienced in handling difficult customer  and demand on technical issues.
Experienced in developing the team management and interfaces to foreign management.
Familiar with simulation software such as ANSOFT(Designer, Ensemble, HFSS) and ADS.
Familiar with different kinds of RF test instruments.

2 U' x$ t# {0 J0 a; s# \3 rAny Other Special Skills / Attributes :
, u" l, n. m% n/ Z' |5 M9 V9 W7 wFamiliar working in a multicultural environment . ( eg. Western cultures )
Self motivator and able to work independently.
Good communication and interpersonal communication skills.
( f" C% S2 \0 \/ M" s, l4 J1 j' hReading/Writing fluently in English and Chinese.
( t* t5 V, E0 _' l4 D* A" OGood experienced in RF test and lab instrumentations.

ranica

SR Application Engineer
9 T) v7 v' g3 u) s- s5 d公      司：A leader in high performance analog and mixed-signal IC design
工作地点：北京

3 g% b" {) J# `, ~9 R" ]' U岗位职责：  
1、 与市场销售团队合作，负责公司产品的售前及售后支持，包括拜访客户，帮助客户了解并认可公司产品，客户现场产品支持与调试；  
* h9 c. i$ j* H0 e* u0 P( D' i2、 负责公司新产品的测试板卡软硬件设计,新产品的测试、分析及可靠性验证；协同生产外包部门作供应商的选择及质量管控；  
4 J6 O# d" k8 y' n2 `, B3、 负责处理客户投诉及产品品质的不断提升；  
+ }0 T- t' f+ L5 ?1 C4、 保证公司质量体系的正常运转及不断改进;  
( j4 B" A9 F& j7 i- H0 A. c5、 根据芯片验证与系统要求制定产品中测及量产测试方案、建立测试环境、编写测试规程、执行测试任务、分析测试数据、出具测试报告;  
$ S* }. D" g3 E1 N6、 设计芯片量产测试流程，跟踪量产测试进展，根据测试数据分析产品良率；  
7、 对客户应用中反馈的芯片问题进行分析解决、维护和系统优化；  
7 t8 M8 {' @2 u2 j! a6 p2 d1 \7 b. ]8、 完成产品的中测、封装以及成测规范的制定 设计IC测试电路，应用电路的原理图；  
- A: X; f% u; f% Q; ^9 s9、 对各个产品的量产状况进行跟踪，及时解决出现的问题维护生产的正常； 针对产品特点，提出相应的可靠性测试方案，并负责测试任务的实施； 对生产过程中和客户使用过程中确认失效的产品制定失效分析方案； 总结实际工作积累的经验，提出适合公司产品的测试规范。

ranica

任职要求：  
1. 本科以上学历，电力、电子、通信、工业电气自动化、计算机硬件等专业；  
2. 具有4年以上半导体及相关行业从业经验；  
2 H; N: h" h  r; l3. 具有无线通讯基站、直放站、安防监控系统、光端机开发经验或相关市场半导体集成产品技术支持经验者优先；  
4. 具有工业、医疗及仪器仪表等相关开发经验或相关市场半导体集成产品技术支持经验者优先；  
5. 从业集成电路IC测试行业并具有IC测试系统开发经历者优先；  
6. 了解当前IC测试系统的行业背景及技术前沿，并掌握相关核心技术；  
7. 具有丰富的模拟电路设计经验，有模拟及混合信号器件的研发经验,具有高速模拟及混合信号集成电路测试系统的开发经验优先；  
' O2 `! Z- u" u0 [# ]8. 具有CPLD、FPGA的应用经验，精通FPGA编程及器件仿真等开发经验优先；  
% l" U6 v& ^9 [3 n% s9. 精通Visual C、Visual Basic 编程技术，精通MATLAB、LABVIEW，有上位机系统测试软件开发经验优先；  
2 {/ U% Q$ Y# M8 S; X8 t5 S10. 有熟练使用网络分析仪, 频谱分析仪,函数发生器,逻辑分析仪,示波器等试验室基本仪器设备经验优先；  
3 ]5 |% g  q  O& n1 Z7 ?11. 优秀的复杂事务应变能力，能独挡一面，有支持销售团队的经验；  
) l5 d6 G. v6 N8 T% s12. 优秀的沟通和谈判技巧，愿意承担一定的压力；  
& E. w# q2 N2 b* p: Y13. 性格开朗外向，良好的人际交往能力,良好的整体协调能力；  
14. 良好英文读写能力；

ranica

SW Support
( V/ q1 `) |9 V' ?8 M. Z" z公      司：Leading local luxury woman's clothing company
- w3 N& a3 q4 t- s工作地点：上海

4 Z, P7 F) H: U3 D: V( V; l4 h4 zResponsibilities:  
( {9 n: l& T- u9 k1 }6 @/ e$ c  The job mainly response for:
  * Daily support of China IMG customer with  based SoC design. Answering technical questions regarding to  products including: simulation,  SoC bringup, OS/Linux bringup, Android. Troubleshooting problems that customer has got during the SoC design, bringup and product integration. Tracking customer project status.Travel needed to resolve customer critical issues on site.
8 K. B+ Z: A0 A- n% n * Training Customer with  IP technologies, Write Application Note for customer to  use products.
- H  S: L/ S9 J; E, v" ~2 g5 N4 r * Feedback customer engineering issues, ecosystem issues to Marketing/Engineering/Sales  
3 J: b* H5 l! X* B2 ^5 [" ^4 b: u+ k- ]( B * Support Sales/Solution engineer with technical evaluation of  products.

Requirements:
Strong background in Computer Architecture, understanding of RISC architectures and programming model (MIPS architecture prefered)
5+ years of software development with C/C++/asm experience is a must. Understanding Linux kernel and its architecture dependent implementation on at least one architecture. (MIPS prefered). Familiar with at least one RTOS.
$ C& }! y9 J! n8 I6 w Familiar with GNU tools, knowledge of JTAG debugging interface.
; E' D! n; m& @4 e( SExtensive knowledge on various technologies like networking, web, virtual machine, binary translator runtime middleware, Android.
7 \0 I$ B3 _" W8 s3 M3 T Fast learner. Self driving, be able to work both in a team or individual.  
" }2 E$ I. R3 j/ ?  Q1 Q English for both speaking and writing

ranica

Product Engineer-芯片物理设计
公      司：A famous IC company
工作地点：上海
: {/ ^7 Y* p: ]) m
Position Summary:  
Develop andmaintain co-simulation tools for IC-package-PCB power and signal integritysolution
Essential Job Functions/Accountabilities:
1. Customer Support
1 J. a/ s6 T- n! n2. Function Specification
- c1 Y% }% J$ M( j3. Bug/enhancement Testing
. {% [/ W- ?, C% d4. Manual and Application Notes Documentation

Minimum Requirements/Qualifications:
Knowledge in VLSI designs and electronic circuits
Experience in back-end place and route design flow
Experience or having some knowledge in front-end RTL coding
6 P1 s+ y: m; w9 T9 Y Experience in using EDA tools in some of the following areas:
     - LEF, DEF, GDSII
     - Liberty, Static Timing Analysis
( Y+ |1 W% d  S! v( V0 Q     - Parasitic Extraction, SPEF/DSPF
     - Spice simulation
Computer programming skills using Perl or TCL.
2 t9 V3 e# B0 f* Y6 g: a) [ Good communication and problem solving skills.
4 }. t5 a' _5 h$ Q Team oriented with a desire to learn.
Able to work independently at various levels of sophistication
9 J9 ^# j) N, m2 K0 E M.S.E.E. or above. Must have at least 3-year related working experience
6 {2 h$ t3 F' b# @Non-Negotiable Hiring Criteria:

ranica

Electric & Communication Engineer

公      司：A famous European IC company
; J* f* W+ S6 h$ |) U- c工作地点：无锡

! Q/ y4 R" M+ w. t# j! WRoles and Responsibilities:
4 T* |' C/ H$ f; N; l6 u- Set up and maintenance telephone system with help of QI.  
2 \" k# w; g" l1 e- Keep both inside and outside equipment in good condition.  
6 y9 j# \% g/ f% ~7 n3 \- Reset up the communication equipment according to the requirement. If necessary, arrange the post, transport and other things.
- Plan, develop and maintain fire alarm system and plant security system  
- Decide the telephone system with help of QI.  
- Call outside service and control the cost.  
% E' j. y5 X- m& ^1 p: g$ ?1 A; |' V- Make maintenance plan and budget plan every year.  

4 i# V  R6 S. B5 b" q$ HQualification:
- Bachelor or above of electron-communication.  
- Good English skill (reading, writing and speaking.)  
- Two year experience for relevant work.

ranica

Maintenance Engineer

公      司：A famous European IC company
工作地点：无锡

Roles and Responsibilities:
- Responsible MAE maintenance structure construction/updating, and lead its implementation/confirmation(TPM with 4 Pillar: Autonomous maintenance; trouble shooting; Preventive maintenance; MAE improvements)
- Responsible MAE spare parts structure construction/updating.  
$ }3 S+ @: r* l$ ~5 R- Leading the key malfunction analysis and create the maintenance report; Guiding maintenance technician for trouble shooting( 7D per week, 24H/Day consulting available for critical on line trouble shooting).
3 O2 X5 N4 H+ k) T4 A- Maintenance competence build up and documentation, supporting of competence distribution within maintenance technician group(like hold training).
& n; V& q0 b/ J# z2 l- Create and maintain the technical communication with MAE supplier/ lead plant/ maintenance service supplier
1 }8 A) `; A1 Q! Q. V' K& m- Working with TEF3 KPI project like maintenance cost reduction and technical loss reduction.
5 ^/ v+ e1 L) n) S1 c
7 j$ k3 k/ t4 [( ?8 p, `Qualification:  
2 g# w. N/ X5 [- {- Bachelor or above with mechanical/electrical major.  
- Good English speaking/ reading/ writing. Better German as second foreign language.  
- 2 year or above working experience on maintenance area

ritaliu0604

SERDES设计经理
' Q$ P$ E+ A+ E! u
公      司：A famous IC company
工作地点：上海
4 d8 D4 W$ ?: g0 P5 l: k
- t4 w, C% w& D' O- X" K* _主要职责：
1. 全面负责SERDES设计；
5 E: K9 U/ d. p) \9 e; ?# S% @2. 设计实现SERDES所需的模拟电路模块和全定制电路模块；
3. 参与芯片的Tapeout工作过程；
, d3 M: {' S" s) N; g7 K& [/ |4. 参与芯片的Bringup过程。

职位要求：
1.  经验要求：
" {8 d" u3 S6 I1) 五年以上全定制SERDES电路设计方面的相关经验；
2) 从芯片设计到投片以及芯片系统调试的整个流程的经验；

2.  专业技能：
1) 熟练掌握模拟集成电路和CMOS全定制集成电路模块设计流程和方法；
2) 深入理解集成电路工作原理，熟练掌握Spice等相关工具的使用；
3) 熟悉集成电路中重要模拟器件的工作原理及其实现
/ g  k: q- c5 N3 Q- t4) 对集成电路制造工艺及制造过程有全面地了解；
5) 掌握模拟集成电路的测试原理、方法。
1 }4 p2 F! `# d- V! G2 e
6 B& }9 B8 ~, [% S' J1 }# H电子工程、半导体物理与器件、微电子学或相关专业硕士及以上学历

amatom

ADI整合型收發器與支援生鏈帶動次世代軟體定義無線電設計
-          RF 高靈敏收發器提供了比同級產品高達三倍的雜訊性能，並且顯著降低物料成本。
-          設計件、FPGA的快速原型產品構環境減少了設計的時間與風險。

: l: N1 @0 k) N; a0 Q(2013年10月23日，台北訊) 全球信號處理應用高性能半導體領導廠商Analog Devices, Inc. （NASDAQ：ADI）美商亞德諾公司，今天發一款針對軟體定義無線電（SDR）應的革命性解決方案。為了實現運作於寬廣圍的調變架構與網路規格等可編程無線電用所設計，像是國防電子、儀器設備與通基礎建設等，AD 9361 RF 高靈敏收發器提供了同級產品中最佳的性能、高合性、寬頻運作以及彈性化等特點。AD 9361 受到廣泛設計資源的支援，能夠加快上市的時間，其中包括軟體設計套件與FPGA夾層卡（FMC），得以快速的開發出軟體定義無線電解決方案。若需要更多的相關資訊，請點擊此處觀賞影片。

$ `# J+ M; x, A+ rAD 9361高靈敏收器是一款搭配強大開發套件的完整RF收發器單晶片解決方案 – 它是RF架構設計師的夢想元件。” ，美商國家儀器子公司Ettus Research?總裁Matt Ettus表示，“們正在將 AD 9361與Xilinx件在我們的USRP B200以及USRP B210中搭配使用，藉以開發出業界當中具有最高性能而且彈性化的軟體定義無線電解決方案。”
) V2 u/ z. d8 H2 U- b/ w! }8 B
* e4 r+ F% B: p) D- CAD-FMCOMMS2-EBZ-FMC 板 為設計者提供了一個快速開發原型產品的環境，能夠支援多重通訊協定，包括了大部分的授權波段與未授權波段。
+ x* A$ N, q) @
“AD 9361在編程方面的彈性以及組態設定能力，再加上低功率軟體可設定無線電的彈性以及其小巧的佔位面積，能夠實現設計多功能性的全新水準。”，ADI技術長 Sam Fuller表示，”這項術上的進步受到了具有同樣先進等級客戶態鏈設計支援特點所支援，能夠大幅縮小市時間的限制，同時降低專案的風險。”
) k8 i! h' g1 X2 G5 V$ J
- `: r8 U' R5 g9 Z/ F關於AD 9361 RF高靈敏收發器
. @/ Q) `8 c* H/ o" H2 I; u5 m" M運作頻率範圍在70 MHz至6 GHz之間的 AD 9361是個完整的無線電設計，在其單晶片當中結了多重功能。此款RF高靈敏收發器中整合了RF前端、彈性化的混合信號基頻帶域、頻率合成器、兩組類比數位轉換器、及兩組直接轉換接收器，能夠簡化設計與少物料成本。AD 9361支援從低於200 kHz一直到 56 MHz通道頻寬，而且具有高度的可編程性，提目前市場中最為寬廣的動態範圍。

兩組獨立的直接轉換接收器具有最為先進雜訊係數與線性度。每組接收子系統都包獨立的自動增益控制、dc偏移校正、正交校正、以及數位濾功能，因此省去了在數位基頻帶所需要的些功能。AD 9361具有可以從外部控制的彈性化手動增益模。
  U9 m  e+ l, z6 `
8 e/ t* p5 w! y* a- i; O6 h- S* m3 z/ `/ h每通道兩組高動態範圍的A/D轉換器將接收到的I與Q信號予以數位化，並且使它們通過組態可設定的降頻濾波器與128-tap的FIR濾波器，進而以適當的取樣速率生成12位元的輸出信號。發射器使用直接轉換架構，能夠以超低雜訊實現高調變精確度。

可以取得AD 9361計資源：軟體設計套件以及FMC板
除了 FPGA夾層卡之外，ADI還提供了廣泛的AD 9361設計資源，其中包括Gerber檔案、式碼參考、Linux示範應用程式與驅動程式、以設計支援包，目前已經可以提供 下載。

ranica

analog engineer

公      司：a top 15 semiconductor company
( R; _: L/ a4 Y6 t" u工作地点：上海

Job Description:  
" ?8 d8 u; h/ k, n( t5 F3 `Take charge of Key IP development for analog/mix-signal IC design project ensure the quality;
# T! T, y# d9 QProvide technical guidance  to layout; application and evaluation teams;
Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
* Y! W# V0 O) T5 Q+ sDeliver the design documents including the design SPEC, review files, evaluation plan
% R, [9 _8 K' H* \7 \) s! Q8 }& ACapable for debugging and bench evaluation

Requirement:  
  I: d: u& b0 n/ t  c& HSolid understanding on analog circuit analysis, verification and IC design technology
Experience using analog simulation tools  
) ^6 F5 c2 I% ^5 v9 y. L2 RGood silicon debug capability
Excellent verbal and written communication skills  
, [- s; e0 q; XAbility to work effectively within a team environment  
- G' \9 b& j  I) y: \% s: a  
Qualification:  
8 y! ?- `0 q7 W; k4 lMS degree with 3+ years experience in IC industry
3 i: A) ~/ ^8 b( tADC related products experience is preferred

ranica

Senior Design Manager
" C; n4 t; o& U) Y9 q4 H1 O
公      司：A famous IC company
. y! u8 V1 E- c8 ?( s9 B/ X- R工作地点：上海

0 |  {: u$ U/ W, B& m6 C! VDuties  
0 B/ ~9 {6 Y8 e1 v        Analog IC circuit design, simulation and verification  
        Design analog products and blocks such as high current, high voltage DC-DC etc.  
        Design of the switching power IC, Charger, Load switch etc.  
        Evaluation, simulation and analysis of power architectures and circuit topologies  
% Y; T) r4 M# _# g        Mixed-signal circuit design, verification  
7 q) `! C1 P. `        IC layout including floor planning, DRC, LVS, and LPE  
        Work with application and testing engineers to define optimal characterization and testing solution  
        Work with product definers and product engineers in full product development flow  
        Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
2 }1 R" Q" E, t! b        Building and creates strong morale and spirit in his/her team.

ranica

Requirements  
        Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree  
        At least 5 years  leadership experience in leading a mid-sized team  
0 ~& c! r6 R5 H- `$ G& n        Strong knowledge in analog CMOS and Bipolar IC design  
        Working direct experience with switching power supplies, DC-DC converters, Battery charger,  and their various topologies  
* D. h4 m" W+ W! K5 Q$ }5 C        Theoretical understanding of the power electronics, switching power supply topologies  
        Prior experience with power management related IC design a strong plus  
2 k: }) n6 k7 o* I& O        Knowledge in analog IC layout  
/ p% w, p5 q7 |  n  v# s        Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus  
        Result driven and can effectively dealing with ambiguity  
        Excellent written/oral communication and presentation skills.   
2 T+ Q; y: Y! p4 |6 D. L; f4 A        Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.

mister_liu

模拟电路设计主任工程师

公      司：A famous IC company
  e- [! ]2 N, a工作地点：苏州
4 b0 V: h! b- z+ Q) C7 o
: t: P! |6 l6 n# f9 u. i9 y' Q; l岗位职责：
' K( |* q  {4 a8 u0 R! }9 w1、负责高速SerDes接口相关技术开发，承担核心技术攻关职责；  
2、负责SerDes接口相关功能模块及整体架构设计，指导高级工程师进行功能模块设计；  
8 E# [6 a$ S( v9 W+ x3、配合相关部门进行芯片Debug与测试，能协助解决芯片量产过程中的问题；
4、负责SerDes设计相关技术培训，增强团队整体技术能力；

任职要求：
1 g) n" v: [2 R2 X* L5 Q$ t1、硕士学位，8年以上相关行业工作经验；或博士学位，5年以上相关行业工作经验；
2、熟悉PCIE2/3 PHY、SATA3 PHY、MIPI M-PHY等相关架构与协议；有高速SerDes开发经验，至少能独立完成或负责一项功能模块设计，如PLL，CDR和CTLE/DFE等；有Marvell、Texas Instruments、ADI等知名模拟电路公司设计经验者优先；有SATA、PCIe PHY相关设计经验者优先；
; e( Z7 V, h$ t: h- A& p3 H! L4 W3、熟悉模拟IC设计主流环境与工具；  
5 \5 H9 Z* M8 ~; \3 \4、熟悉模拟电路设计基本理论，熟悉信号与系统，数字信号处理等理论；

ranica

Staff Analog Design Engineer
公      司：one famous IC company
: D( ~2 l8 ?) U/ l" v4 x工作地点：上海

2 M% a$ |$ P, o8 O* QResponsibilities:  
--Work with design team for new product development & assist layout designers with product layout, conduct lab experiments and bench testing and evaluation;
--Support test & product engineer with chip debugging, failure analysis, characterizations and product release efforts. Assist vendor to support ongoing product development.
) X' ^5 j  h4 q# _% X. S
6 K' A$ L$ I4 p4 u' tQualification:
--Minimum BSEE/MSEE preferred;
--4+ yrs. of experience on analog IC design area;
: e( J) j8 f2 m. g1 z--Knowledge of MOSFET physics, semiconductor process and layout;
--Experience in analog blocks design, such as voltage reference, opamp, comparator, etc;
--Experience in PLL design is must to have;
$ a1 }' |0 G' h0 k0 E--Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator) and Virtuso;
  X: v8 m! Q8 V1 Q--At least one design finalized in silicon preferred.

ranica

analog engineer
公      司：a top 15 semiconductor company
工作地点：上海
1 A! Q) P2 N# G0 g/ S2 z
Job Description:  
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality;
* z$ [2 c1 \9 ZProvide technical guidance  to layout; application and evaluation teams;
: l5 F7 t& F5 M$ _& Z# t& bEngage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
/ {/ \8 V3 t* b: o3 `/ V& o8 XDeliver the design documents including the design SPEC, review files, evaluation plan
Capable for debugging and bench evaluation

5 b5 T- M, N/ F9 @Requirement:  
Solid understanding on analog circuit analysis, verification and IC design technology
Experience using analog simulation tools  
Good silicon debug capability
# I3 h2 x8 k  {( NExcellent verbal and written communication skills  
Ability to work effectively within a team environment  
  
" G" S$ C) M8 |' G! d  m2 f8 aQualification:  
MS degree with 3+ years experience in IC industry
: m% V$ t6 m" H, c9 I$ y- c! X1 ~2 G4 bADC related products experience is preferred

ranica

analog engineer
6 N: z0 G* w. s! M# X
/ ]% o9 j# R7 j/ {. P公      司：a top 15 semiconductor company
5 p- {/ c: U% _0 ~, w* l0 G工作地点：上海
% a/ P+ e" Z3 d" W) r  d
- t9 q& D: Q$ u/ n" K  qJob Description:  
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality;
Provide technical guidance  to layout; application and evaluation teams;
- Q0 b- `4 j4 m" V6 ^Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
- x4 c- |9 y" D! t) HDeliver the design documents including the design SPEC, review files, evaluation plan
6 U  F( P) E6 Y! O. uCapable for debugging and bench evaluation
1 G, h3 Y7 E  c; x
3 S3 P$ U4 Z, h! m6 l! Z; sRequirement:  
Solid understanding on analog circuit analysis, verification and IC design technology
9 o; s. J1 A/ ?% r! ~Experience using analog simulation tools  
Good silicon debug capability
+ O( a" t4 Y$ oExcellent verbal and written communication skills  
# n: O8 K  }4 W- ~& U' pAbility to work effectively within a team environment  
/ X& l! u5 C8 U  
( ?6 Y6 {) X; d2 H4 J! A; V1 Q, t( ]Qualification:  
5 {  l$ \% f) Q; K2 E4 fMS degree with 3+ years experience in IC industry
9 E7 n2 D& @+ U! n6 A! u4 uADC related products experience is preferred

globe0968

Senior Design Manager
公      司：A famous IC company
工作地点：上海
+ J& }8 ]. h  k$ C+ X
Duties  
- j# V* U3 L* @2 m" c- A        Analog IC circuit design, simulation and verification  
" t" Q, O2 ]# h0 f        Design analog products and blocks such as high current, high voltage DC-DC etc.  
        Design of the switching power IC, Charger, Load switch etc.  
3 W% R  y$ p- x! Q        Evaluation, simulation and analysis of power architectures and circuit topologies  
0 N* \! a0 Z! u        Mixed-signal circuit design, verification  
        IC layout including floor planning, DRC, LVS, and LPE  
! I' A, i. V- a" x7 f2 [        Work with application and testing engineers to define optimal characterization and testing solution  
* O. ~  c( ~" h" Y# V- v        Work with product definers and product engineers in full product development flow  
( N3 w3 |7 A& o# V/ I        Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
' C$ Y% b1 J3 j1 H        Building and creates strong morale and spirit in his/her team.

- T3 V/ e# K8 y; }; uRequirements  
6 ^( m( l2 L4 U1 S        Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree  
        At least 5 years  leadership experience in leading a mid-sized team  
& \) O, \8 N- E- x        Strong knowledge in analog CMOS and Bipolar IC design  
        Working direct experience with switching power supplies, DC-DC converters, Battery charger,  and their various topologies  
        Theoretical understanding of the power electronics, switching power supply topologies  
        Prior experience with power management related IC design a strong plus  
# R& R! K( R: g) C% @- A: w        Knowledge in analog IC layout  
        Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus  
        Result driven and can effectively dealing with ambiguity  
        Excellent written/oral communication and presentation skills.   
        Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.

innoing123

项目经理
" Y- F& u% n9 G- {公      司：A Chinese integrated solution supplier
工作地点：深圳
) W, z# n8 o5 {) i/ K- C- r- Q
1 I+ X& G: ?0 I- S$ X" t8 R0 g职位描述：
1、负责完成电容触控、可穿戴设备、智能sensor领域的芯片固件方案；
2、制订项目计划并负责跟进，安排团队成员工作；
" q* n# h; e/ l! o! X' p3、分析市场需求和产品功能定义，协调跨部门工作；  
4、参与硬件方案的设计和评审，负责系统优化；
. |7 f$ t9 U: t* b
+ T- y8 Z$ a5 ]# }; V7 @任职要求：
1、电子信息、计算机等相关专业，重点院校本科或以上学历；  
) l# g4 {: A0 z5 j9 w, g/ m2、3年以上芯片固件开发经验；  
3、熟悉数据结构、掌握一些常用的算法分析和设计方法；  
4、良好的沟通表达能力和团队协作能力