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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-9-27 14:10:16 | 顯示全部樓層
Staff Engineer-RF  J2 G. b1 \2 r/ q' i; |( v9 N
9 e1 Z) s0 I/ M
公      司:A famous IC company
' j; X' f) k$ V0 p  r" @工作地点:上海1 i$ ^" Y1 R. a( A

% W+ t4 x$ I% j. B5 ]" ~1 ]/ tJob Description:
- K; y4 T! d& cRole as RF Power project manager for Shanghai Development Center ( SDC )
8 G0 U+ t4 |, l9 N3 x4 I9 bMay be considered as team lead if relevant team leadership experience are evident.
- \/ }# l$ W$ f( n7 C. M3 UInvolved in installing and enforcing design rules, flow and milestones checks for SDC.   H  V$ k$ W, V2 G+ J
Able to provide technical guidances in RF Power modules designs( for example, RF Power module designs in the range of 400Mhz -2700Mhz)  and Doherthy designs.
& |7 E; E, @2 `0 C  U) xDriver for technical customer interface for Design In and Post Design Win activities.
+ y3 o  k$ Z4 b  ?Proactive in ensuring successful project execution ( cost, schedule and efforts )
4 f3 f& n  W# y5 j2 v2 d* @Provide report to management of project and customer technical issues status .
7 X0 g% v3 l3 g0 gManage project issues with proactive tracking of issues and defining effective countermeasures.
; D9 j2 _7 k, Y0 c. L- N0 F' ~& ZWill required Hands On in PCB and System circuit design together with the junior team. : _# A2 [. w& s- @& i
Involved in Product definition of new RF Power module designs.
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2#
發表於 2013-9-27 14:10:21 | 顯示全部樓層
Qualification :
( J9 c$ z3 J  N7 s1 Q' s# y& \. G6 rBachelors/Master/PhD Degree in Electronic Engineering ( specializing in Electromagnetic Fields ,  Microwave & in RF Power )
1 n* a* z$ ?. I: L" k1 [# ^" n9 N; s1 ^
Experience: ) ^8 r  a, m/ ^8 U$ ?' N2 W8 m) z
At least 10 years of experience in RF Power circuit design and application/system development.
3 I. C6 t1 B, h7 oExperienced in RF power amplifier designs , Doherthy amplifiers designs and RF POwer systems development.
. A) f- N" m2 E% v8 x( D  M% |: QExperienced as project manager managing projects in RF power designs with multisite overseas development teams." q" p: X' \" ], n; ^( ]# M" y' z
Able to translate customer requirements to specifications and to designing final products/systems according to the customer needs.
* r/ V9 h* U. _8 Z( d1 vDiligent in following company design rules, verifications and milestones checks for all phases of development.
6 b! ]) W7 |8 g/ W/ U5 ^Familiar and experienced in handling difficult customer  and demand on technical issues. ( u2 n# g5 W% b- N: s  r3 x" x
Experienced in developing the team management and interfaces to foreign management. 0 X3 L+ U  j. [
Familiar with simulation software such as ANSOFT(Designer, Ensemble, HFSS) and ADS.
; v4 ^! y" L. m' V/ c% R0 GFamiliar with different kinds of RF test instruments.
' L2 M8 O+ a7 _3 D8 ]8 [- e* F0 J$ w/ v
Any Other Special Skills / Attributes :
0 K% t+ s$ f6 R# IFamiliar working in a multicultural environment . ( eg. Western cultures )
* ?6 x$ x# p/ O) D5 Y/ ^Self motivator and able to work independently. 2 u6 q: Y" n3 N' Y; z
Good communication and interpersonal communication skills. 2 o2 H, q& l" u8 {3 g
Reading/Writing fluently in English and Chinese. " T5 Z4 g) j9 L* Y
Good experienced in RF test and lab instrumentations.
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3#
發表於 2013-10-9 14:01:50 | 顯示全部樓層
SR Application Engineer
  e2 W8 G2 p+ h# {公      司:A leader in high performance analog and mixed-signal IC design( C2 r! J8 [% j6 m0 W9 ^8 X. _
工作地点:北京5 W# k! l6 i% E( x- E! O

% p0 {+ J3 I5 j+ [" J. ?岗位职责:  ( v& ?! u; j0 I9 l
1、 与市场销售团队合作,负责公司产品的售前及售后支持,包括拜访客户,帮助客户了解并认可公司产品,客户现场产品支持与调试;  
# q! e( ^. ^' q$ F. u  T# b* H2、 负责公司新产品的测试板卡软硬件设计,新产品的测试、分析及可靠性验证;协同生产外包部门作供应商的选择及质量管控;  + z% H; K8 `5 a( n  g" Z
3、 负责处理客户投诉及产品品质的不断提升;  : ^) C; s4 x6 l. T  Y7 N
4、 保证公司质量体系的正常运转及不断改进;  
* H; E7 a3 Q& C$ l- ]9 {6 A% `7 X5、 根据芯片验证与系统要求制定产品中测及量产测试方案、建立测试环境、编写测试规程、执行测试任务、分析测试数据、出具测试报告;  
. K  f9 v' X; n) i* E6、 设计芯片量产测试流程,跟踪量产测试进展,根据测试数据分析产品良率;  5 E7 S! J* B2 E2 W* r; J% ^
7、 对客户应用中反馈的芯片问题进行分析解决、维护和系统优化;  
* W* R6 r9 ^6 B/ K- D0 G  s0 A: Y. K8、 完成产品的中测、封装以及成测规范的制定 设计IC测试电路,应用电路的原理图;  % W7 t) l- r. G6 X; U9 B! j
9、 对各个产品的量产状况进行跟踪,及时解决出现的问题维护生产的正常; 针对产品特点,提出相应的可靠性测试方案,并负责测试任务的实施; 对生产过程中和客户使用过程中确认失效的产品制定失效分析方案; 总结实际工作积累的经验,提出适合公司产品的测试规范。
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4#
發表於 2013-10-9 14:01:56 | 顯示全部樓層
任职要求:  : I0 ~( A2 r" o; C" U
1. 本科以上学历,电力、电子、通信、工业电气自动化、计算机硬件等专业;  ; {+ T8 C8 t9 h9 D) t! ?! ]$ ]
2. 具有4年以上半导体及相关行业从业经验;  
, a3 k7 O+ u0 y- w, ^3. 具有无线通讯基站、直放站、安防监控系统、光端机开发经验或相关市场半导体集成产品技术支持经验者优先;  3 S5 k- W; Q# D6 {. W4 V3 F8 u
4. 具有工业、医疗及仪器仪表等相关开发经验或相关市场半导体集成产品技术支持经验者优先;  % q9 Q2 A% s# c) z/ D0 Z3 h
5. 从业集成电路IC测试行业并具有IC测试系统开发经历者优先;  % I+ r8 F( Y; |- n6 [
6. 了解当前IC测试系统的行业背景及技术前沿,并掌握相关核心技术;  + H9 [7 z# z% Y* t% t& Q3 W
7. 具有丰富的模拟电路设计经验,有模拟及混合信号器件的研发经验,具有高速模拟及混合信号集成电路测试系统的开发经验优先;  " f+ U& g) K6 M
8. 具有CPLD、FPGA的应用经验,精通FPGA编程及器件仿真等开发经验优先;  0 `/ f1 t# n1 `7 `! U* z5 R7 I2 R
9. 精通Visual C、Visual Basic 编程技术,精通MATLAB、LABVIEW,有上位机系统测试软件开发经验优先;  
& Z+ Y& f  Q; r: i10. 有熟练使用网络分析仪, 频谱分析仪,函数发生器,逻辑分析仪,示波器等试验室基本仪器设备经验优先;  
2 V; c1 N% C  M/ w$ t' L11. 优秀的复杂事务应变能力,能独挡一面,有支持销售团队的经验;    T6 H2 \" B' a6 P
12. 优秀的沟通和谈判技巧,愿意承担一定的压力;  
8 p  J0 o9 P# k( {13. 性格开朗外向,良好的人际交往能力,良好的整体协调能力;  9 Y' U- w( u2 G0 p# k' }
14. 良好英文读写能力;
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5#
發表於 2013-10-9 14:02:40 | 顯示全部樓層
SW Support( y9 c  a: q: C, {
公      司:Leading local luxury woman's clothing company2 p/ G6 C! c- ?8 I4 x; `& W/ O# {7 q
工作地点:上海, e3 D# g! ?2 R, W8 I& N4 x# J
' K; P( m# M6 i
Responsibilities:  
: @8 n3 N! w$ Y: {, u" x6 }1 j  The job mainly response for: 2 V8 k7 D7 w9 l+ _. Z! g8 d
  * Daily support of China IMG customer with  based SoC design. Answering technical questions regarding to  products including: simulation,  SoC bringup, OS/Linux bringup, Android. Troubleshooting problems that customer has got during the SoC design, bringup and product integration. Tracking customer project status.Travel needed to resolve customer critical issues on site.
0 c+ m7 o4 `& @  S3 _+ [" y7 A * Training Customer with  IP technologies, Write Application Note for customer to  use products.
( `" h8 V, ?3 e4 U$ |7 g- N/ r * Feedback customer engineering issues, ecosystem issues to Marketing/Engineering/Sales  ) c8 k9 T7 Z, A' |& z
* Support Sales/Solution engineer with technical evaluation of  products." J( u5 |; s( r  C# c

. [/ c0 g* Q# m, _; X1 h* D. MRequirements: # |4 H0 J. _5 L3 V1 b
Strong background in Computer Architecture, understanding of RISC architectures and programming model (MIPS architecture prefered)
% I/ `6 K. F& e; e! y( M8 ~& }% e6 P8 w 5+ years of software development with C/C++/asm experience is a must. Understanding Linux kernel and its architecture dependent implementation on at least one architecture. (MIPS prefered). Familiar with at least one RTOS.
0 c9 O7 e0 a4 c  j: {- D$ u* p( O Familiar with GNU tools, knowledge of JTAG debugging interface.
; i4 z% C1 ^: Z: v" sExtensive knowledge on various technologies like networking, web, virtual machine, binary translator runtime middleware, Android.
6 T8 H' x, P* g) k& z. g8 n: M6 S Fast learner. Self driving, be able to work both in a team or individual.  
) |( |& @/ e3 ?, ^  X9 I& e; t English for both speaking and writing
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6#
發表於 2013-10-14 15:55:59 | 顯示全部樓層
Product Engineer-芯片物理设计
- y' N3 Y) k2 B+ J5 g公      司:A famous IC company
" S8 N4 l* h6 T) e" e% Z工作地点:上海
4 j1 T! y  x' N, f; m7 q& Y$ Z, M# B# ^2 n/ ^" D9 S3 Z! p
Position Summary:  ( a/ e; u+ q$ n; X: ?( R# D
Develop andmaintain co-simulation tools for IC-package-PCB power and signal integritysolution
+ l% J9 e( b0 b" }Essential Job Functions/Accountabilities:
# J, f4 P3 b" _5 Y2 S9 }1. Customer Support : d4 c" U4 \) j' {
2. Function Specification
. D/ @/ x% z) |* {( N5 c+ P  Z3. Bug/enhancement Testing 0 c+ x8 Y7 F  I. c
4. Manual and Application Notes Documentation
+ L* I8 S8 ~3 [" V3 x, j; F2 e0 z% I2 f" f7 {
Minimum Requirements/Qualifications:
; i& C" S; G5 `3 d  z Knowledge in VLSI designs and electronic circuits
% R, p  p  ]; u4 J% s9 ?6 c Experience in back-end place and route design flow . _9 u# [. `" a$ T$ f
Experience or having some knowledge in front-end RTL coding
. O3 e6 ~5 m9 S/ n/ @. e Experience in using EDA tools in some of the following areas: 4 m5 G; D8 _& _1 i1 T6 F: Z3 L
     - LEF, DEF, GDSII
2 m: v! |8 Y1 w* m7 P8 B     - Liberty, Static Timing Analysis
% ~/ ?, Q4 \  @( o/ ^2 A7 y, `     - Parasitic Extraction, SPEF/DSPF
2 ]) {7 J4 ]% m( K$ P     - Spice simulation 3 J/ o7 e4 q7 n( C1 n
Computer programming skills using Perl or TCL. 4 k7 E3 b8 e# y, D- e; u
Good communication and problem solving skills. 2 \6 R0 P+ h5 [3 r8 e
Team oriented with a desire to learn.
; A) U& l+ e0 N* L6 ~ Able to work independently at various levels of sophistication 7 Z. R. b7 J* p) k2 e1 t0 v3 p. i
M.S.E.E. or above. Must have at least 3-year related working experience , g  C0 d$ Z9 n) T! t, c
Non-Negotiable Hiring Criteria:
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7#
發表於 2013-10-14 16:08:49 | 顯示全部樓層
Electric & Communication Engineer
+ A( _" t7 D9 D1 _; T3 [+ ~4 r4 l4 b: r" `2 j3 ?
公      司:A famous European IC company
2 q1 V) R/ Q4 i% B工作地点:无锡! ]8 u% @/ {& S  U9 k2 D3 d  T

! p+ @4 \/ G5 n- Y$ kRoles and Responsibilities: 4 _# [* B: A- [. Z6 Z! u: p9 A$ m
- Set up and maintenance telephone system with help of QI.  
; ~; f9 w- S+ c0 ~( ]/ o9 d6 p) e- Keep both inside and outside equipment in good condition.  
, O5 E1 X. W- z5 v- B- Reset up the communication equipment according to the requirement. If necessary, arrange the post, transport and other things.
* b7 W& D5 B& |0 A( E1 M; h6 w- Plan, develop and maintain fire alarm system and plant security system  6 j) {6 b. b- U3 J; v; @' t8 B& p' O
- Decide the telephone system with help of QI.  
" k. C8 b% o) [- P( Y% r. }! P) E, }( j- Call outside service and control the cost.  1 k6 ]! D1 f1 d$ \' p4 g6 q8 q6 p
- Make maintenance plan and budget plan every year.  
3 f) n& ^  ^( L$ a! u: z% {) u- p: E: K4 k1 @7 r+ ~
Qualification: * A9 `2 _$ _0 P- d8 l  m- i8 K5 x
- Bachelor or above of electron-communication.  
$ e. w; t* ?/ n- |  ~9 I- Good English skill (reading, writing and speaking.)  3 A" K/ Y$ l/ u) r
- Two year experience for relevant work.
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8#
發表於 2013-10-14 16:09:29 | 顯示全部樓層
Maintenance Engineer2 B1 ?0 X* x6 L( E' L4 T: b

) }: [) e" u) K) d3 [3 C公      司:A famous European IC company
: |7 r; Y  A; v0 H6 M' T工作地点:无锡
. C+ ?6 f& b) O, T! z4 i$ w" k4 I' E. [1 r
Roles and Responsibilities:
4 c7 |/ V# r, R3 D, U0 R; E. |7 ~6 U- Responsible MAE maintenance structure construction/updating, and lead its implementation/confirmation(TPM with 4 Pillar: Autonomous maintenance; trouble shooting; Preventive maintenance; MAE improvements)
7 i2 x0 V8 H/ d( A: f( y( h# @- Responsible MAE spare parts structure construction/updating.  
. r5 [$ @/ A( {- Leading the key malfunction analysis and create the maintenance report; Guiding maintenance technician for trouble shooting( 7D per week, 24H/Day consulting available for critical on line trouble shooting). + T* K" m& ^- U( U
- Maintenance competence build up and documentation, supporting of competence distribution within maintenance technician group(like hold training).
3 d7 ~& I; x: |7 e- Create and maintain the technical communication with MAE supplier/ lead plant/ maintenance service supplier
% H3 @1 d+ y. N+ m3 m  e9 I* [- Working with TEF3 KPI project like maintenance cost reduction and technical loss reduction.
, v6 T) f2 S1 E* P4 g" p" r
4 F$ Z9 f7 y$ `& k. G) AQualification:  
2 l! J8 ]4 E: D6 s, i, u* Z8 j- Bachelor or above with mechanical/electrical major.  " v5 @: [; ^* a  e! u
- Good English speaking/ reading/ writing. Better German as second foreign language.  ' b( c% H! w3 i* c& D" t5 I# x0 d
- 2 year or above working experience on maintenance area
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9#
發表於 2013-10-30 14:14:38 | 顯示全部樓層
analog engineer
& w' ^4 k2 v7 \# v2 X2 {1 u0 Y0 y$ n) X  ]  C
公      司:a top 15 semiconductor company0 L! _" J5 Z" E* ]  A4 f7 `
工作地点:上海
0 _, H) m) W3 j* Y& q( S8 L0 @: G' q  E2 q7 b) V% i
Job Description:    v3 O% R5 ^+ U# f9 A. k+ e% M3 U
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality; . ?) P* {4 x9 z  I
Provide technical guidance  to layout; application and evaluation teams;
6 O! a, X0 S- h2 C: d4 ^: JEngage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
; }0 p- w$ t4 h9 jDeliver the design documents including the design SPEC, review files, evaluation plan ( D1 ]3 L; }' e( S  W/ a
Capable for debugging and bench evaluation 4 @% A* L, r- M( H5 U3 W5 O

) V* O+ l- \! J& S* m6 v8 x. U8 c* gRequirement:  
7 X& x. `& S/ D5 @3 {Solid understanding on analog circuit analysis, verification and IC design technology $ _' S  w3 C+ }6 z
Experience using analog simulation tools  5 W7 @5 F, [0 W7 Z& \" I
Good silicon debug capability
5 Y( N! l( P1 r0 d, Q4 p; ^Excellent verbal and written communication skills  5 B0 I( t3 n& `5 ?/ W. a3 a  P
Ability to work effectively within a team environment  4 L% X- ], X8 U/ \% C
  , h  P5 q6 c: c" b2 Z
Qualification:  
. V- @" L6 J5 u- r# g% EMS degree with 3+ years experience in IC industry + w  N  l, n4 z6 M- \& R
ADC related products experience is preferred
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10#
發表於 2013-10-31 13:51:02 | 顯示全部樓層
Senior Design Manager
" M" Z1 B4 y+ }: s4 X
" y0 v- [5 R$ z( m2 @. C2 j# [& S' E公      司:A famous IC company6 U( @; ?, \( q
工作地点:上海# P& p, K, Y  R8 B  `0 i

9 f$ O. B- ~, L* Z, cDuties  
' K+ K0 i" W, t7 W( \, C        Analog IC circuit design, simulation and verification  ; C8 p$ M# o. O3 L, f, a
        Design analog products and blocks such as high current, high voltage DC-DC etc.  % r, N5 c  H4 @0 @  `6 a: U% |
        Design of the switching power IC, Charger, Load switch etc.  
, U$ P& @6 c5 {( ~5 M8 v        Evaluation, simulation and analysis of power architectures and circuit topologies  % {' Z' G! u1 @# q  N2 O
        Mixed-signal circuit design, verification  4 l# g, m+ [# l
        IC layout including floor planning, DRC, LVS, and LPE  , ?1 {- P9 ^: A1 y. Z; `/ J
        Work with application and testing engineers to define optimal characterization and testing solution  
# ^, F! Q7 v5 p4 Y2 h* D! r2 F7 q        Work with product definers and product engineers in full product development flow  / x, Z3 _$ {4 E7 i# B. L0 n
        Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
- E& o: N( l4 q7 o3 s  |( y        Building and creates strong morale and spirit in his/her team.
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11#
發表於 2013-10-31 13:51:11 | 顯示全部樓層
Requirements  7 Z3 h" e" ?! d1 o
        Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree  - W, `" V3 u+ \, D# u" B
        At least 5 years  leadership experience in leading a mid-sized team  
& c: [9 s3 P* s0 d7 ~: H        Strong knowledge in analog CMOS and Bipolar IC design  
1 S% l/ O# {" [        Working direct experience with switching power supplies, DC-DC converters, Battery charger,  and their various topologies  
! ], K8 ?7 E) M6 c1 I        Theoretical understanding of the power electronics, switching power supply topologies  
+ ^" @: }4 P& a* [5 I$ u        Prior experience with power management related IC design a strong plus  & x# @& f: D" L* J9 h
        Knowledge in analog IC layout  : i5 N- w3 G- L; `7 |+ w
        Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus  
/ o1 H1 }/ y- }$ D3 I" g        Result driven and can effectively dealing with ambiguity  
) n# N- ]7 K7 C, ]) w        Excellent written/oral communication and presentation skills.   
  h, Q6 _! y2 D  F9 I        Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.
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12#
發表於 2013-11-13 14:36:20 | 顯示全部樓層
Staff Analog Design Engineer4 d2 _) f/ {) O: J
公      司:one famous IC company6 ^7 D5 C0 I. F- f
工作地点:上海7 ~% H1 ~1 l6 U  h
$ e6 l5 J' p5 Q; V
Responsibilities:  
. Y) ^) y( _1 Y  X. ~--Work with design team for new product development & assist layout designers with product layout, conduct lab experiments and bench testing and evaluation;- {2 V/ w9 u, N" ]4 V
--Support test & product engineer with chip debugging, failure analysis, characterizations and product release efforts. Assist vendor to support ongoing product development.
: H& s9 s1 r( |2 S  o! {
5 E0 y, v7 z, o, B6 {7 tQualification:
6 G% g' H4 L2 a, Z( _. W  e--Minimum BSEE/MSEE preferred;
0 ^9 M7 B, v2 Y# X--4+ yrs. of experience on analog IC design area; $ i1 B* g& i4 p& r  U6 t: Y, B
--Knowledge of MOSFET physics, semiconductor process and layout;
7 J4 M7 X: U% X5 @- K( G. d+ Z--Experience in analog blocks design, such as voltage reference, opamp, comparator, etc; 2 U7 x+ }$ J3 n& S" ~. l
--Experience in PLL design is must to have;
; n% p5 t. d. t- ~--Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator) and Virtuso;
" }* |; u  \& F( ?--At least one design finalized in silicon preferred.
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13#
發表於 2013-11-13 14:37:57 | 顯示全部樓層
analog engineer
; T3 K1 ^2 i- P  _) y; W) V公      司:a top 15 semiconductor company
% u# B! }* C% z/ O工作地点:上海
, N& x3 D6 b9 M$ f3 |, l6 l5 U  f8 ~
Job Description:  2 }5 T$ C3 G7 A2 b( X9 ~0 G
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality; + U4 m4 t* s1 t3 V3 u( M6 M: [  `
Provide technical guidance  to layout; application and evaluation teams; - w+ H& L- h6 v& `
Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
4 G+ n1 O1 ~1 |) v. t8 Z8 uDeliver the design documents including the design SPEC, review files, evaluation plan
. X& a; N6 \3 l2 l0 W8 x; UCapable for debugging and bench evaluation " X# {! |$ |; B0 }& r# m
6 n  a0 b. D6 r- h. u" k2 u
Requirement:  - W1 w; h; ^# c$ ]9 q; z# w, C
Solid understanding on analog circuit analysis, verification and IC design technology % a. V$ G# k: g7 M
Experience using analog simulation tools  
0 Y) c  x; r6 Q6 GGood silicon debug capability
7 V! y) I/ r9 c* h) QExcellent verbal and written communication skills  
$ H3 q9 R* H. d' VAbility to work effectively within a team environment  - \3 T& A8 ]. [$ }8 @! x
  7 ?6 K6 R7 z# }
Qualification:    ]: T2 J6 s2 H. l9 g; m" [+ {1 o* i
MS degree with 3+ years experience in IC industry ) u* e7 _! e( ~, q
ADC related products experience is preferred
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14#
發表於 2013-11-26 09:33:15 | 顯示全部樓層
analog engineer7 F6 X/ v$ v  d, j- J/ p0 X
1 g% n  x0 g. w# r
公      司:a top 15 semiconductor company( \) f7 T+ o/ u' ~8 z
工作地点:上海& k4 @6 k4 e4 ?
+ f2 a6 `: M4 V5 W4 a  X3 H8 g
Job Description:  
+ d, ^8 A* w- Z4 q* XTake charge of Key IP development for analog/mix-signal IC design project ensure the quality;   o; I) J: {& u0 G6 b4 {5 w3 B
Provide technical guidance  to layout; application and evaluation teams; ' l8 J: x$ V) `2 e) d7 S9 Q; o1 C
Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;* o: ?+ Z$ K; I' Y6 p; h1 I1 q
Deliver the design documents including the design SPEC, review files, evaluation plan # F3 s+ E3 K( c. Z8 L
Capable for debugging and bench evaluation ; e! U; X% Y! n  \) B" Z( V

- U5 I4 R% I2 [/ f0 Z' WRequirement:  
7 E/ s# E7 [( U0 ^; |$ i" OSolid understanding on analog circuit analysis, verification and IC design technology & C7 U% b' b& l6 a* `5 L( k0 L2 Z
Experience using analog simulation tools  % o* L2 B( D, H  ]3 m  }& O# W
Good silicon debug capability
# Y9 ^7 x; B" J/ R& sExcellent verbal and written communication skills  
3 a. W/ j3 u. |- ^8 W  |2 ?  mAbility to work effectively within a team environment  
. w! S- j6 I" @. }% d( {  ! F  L0 O2 L- {  K* l5 C
Qualification:  
" X7 J% ?+ T7 L. z( ?MS degree with 3+ years experience in IC industry
6 l3 S- I! C0 tADC related products experience is preferred
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15#
發表於 2013-12-10 14:51:30 | 顯示全部樓層
模拟电路高级工程师
+ v. }# E. _: D7 D: u5 }/ @公      司:A Chinese integrated solution supplier
$ m5 O! u1 R' F1 U; c2 l. ]4 e工作地点:深圳
# U# e& a4 R# R$ E0 P8 d* \4 w* l2 [9 [. N, i
岗位职责: ! t9 i- N% R8 W2 [* b
1. 微弱信号检测电路研究; - o$ E# K$ t. L3 U# k
2. 芯片方案原型平台设计与调试; & k/ [7 S4 l% G' x
: N! d/ E2 U% ^9 v) Y) X+ Q+ I
任职要求:
' [1 e+ k0 R. y; D+ b1. 本科及以上学历,2年以上相关工作经验;
* m! P2 D; ]; N% V* ?, \2. 通讯、电子、自动化、物理或数学专业;
) c7 q# z3 O3 e* N; T3. 思维灵活,有创新精神;
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16#
發表於 2013-12-10 14:52:00 | 顯示全部樓層
资深硬件工程师
# E. [" S' G- L6 {: Y9 V% c公      司:A Chinese integrated solution supplier
; q" C- h0 }- ?; X工作地点:深圳
) R- N# W& u" S  P" v$ W0 h* T8 L. y5 u$ }( y" @1 j) b% d
职位描述:
& \1 r  M9 g8 v; d8 T' q: m( f1.    电容屏触摸方案硬件应用设计,硬件应用问题分析及解决; & v2 A9 v! P; m0 |0 Z* F5 T1 b7 d- ^
2.    触摸传感器分析及研究;
6 D) {+ j9 _! [7 |% Q3.    日常团队协调及项目跟进工作。0 W- i* w* ?7 m" w* p4 T
# O, r8 L8 j; Q% y
任职要求: ( O+ w: l0 v0 n0 h8 U
1.    微电子、通信、自动化、数学、物理等相关专业全日制本科以上学历,3年以上工作经验
' l+ c/ x+ i9 ]# B- k9 F2.    具有良好的模拟电路与数字电路基础知识
' ?/ d  f8 T$ k. Q3.    具有信号与系统,数字信号处理等专业背景尤佳 3 \+ ~) S7 P6 ?& j9 d
4.    工作认真细致,主动性强,能承受一定工作压力,具有良好的语言和书面表达能力 " L# i4 }4 W" x2 |2 _. j( e
5.    英语四级以上,可熟练阅读英语资料
- S( Z, c% O$ x0 ^! t/ E' m) o4 A6.    满足以下任一项目者可优先考虑:
0 e1 q4 s& ?" _6 ?% ^  V1)    从事过电容屏设计分析工作
" H! y# [3 ?* {) ^2)    从事过微弱信号检测与处理工作 - c! w( H$ H/ U2 {+ P
3)    熟悉FPGA/嵌入式系统工作原理并做过相关开发工作 : F1 C# }& C7 ~# O- j# Y
4)    使用Matlab/Simulink做过电路/信号/控制/数学建模与仿真
2 H8 Q+ F! U9 [* I  M6 n/ q5)    使用SPICE类仿真工具做过电路建模与仿真
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17#
發表於 2013-12-10 14:54:06 | 顯示全部樓層
Principal AMS Physical design engineer9 N% @& m' C5 K# S
公      司:One world top EDA company
3 J' ?+ V3 ~$ {工作地点:上海
0 V1 r/ K; r2 z6 ]2 x: x/ z9 A" Z; P& M
职位描述
9 a. }  L3 m2 o8 v1 g: ^Skillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered.
1 [, u6 T6 u. `7 z+ odepth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc  
  `; q: Q& U1 N# j) [+ d0 NProficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus)
& g, O, m( S; P+ r! J0 |) d# c, l$ Xexperience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry
2 }+ R* M% D& ?2 s2 W3 ]ability to coordinate with the other analog IC circuit layout,  ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
/ V$ C* s" {% c$ cfundamental understanding of IC design technology and process/methodology  ) v9 ]" r: F( s4 g: T
skilled in Analog IC top level chip assembly including floorplanning and block layout
6 s! o" j; q" r& B. C% v5 redicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design;
7 a7 `+ G4 [$ M) nhands-on experience conducting DRC/LVS analysis and recommending appropriate solutions ; y- K9 g1 _  d: m' e) @
solid understanding of IC design technology and process/methodology in AMS layout4 O; U9 n6 C# B- |6 i) k# T/ K

" b8 m0 Q* O* i' e. S& ZPosition Requirements:
* x! {' W/ g6 @0 b) w$ S9 k BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.
) l( O  P, c4 j! a1 L      / a4 j( h0 J9 [$ _
Company Info Type: , R+ b( l1 T& N! `2 b1 o  }
Global Default # W- f2 P/ E, r, X! F6 [* s
  8 B8 O: \  U( @" |
Company Information:
0 K, C4 x1 K' \ xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
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18#
發表於 2013-12-17 10:07:57 | 顯示全部樓層
RF PA设计工程师9 @% O7 q3 ]9 b: y3 e: M3 |
公      司:a fabless semiconductor company( a+ C' D3 e! s
工作地点:北京
3 f- [1 V" B: E# o' v9 R; l2 ^; W/ c$ Z
职位描述:RF PA/Switch新项目研发  
+ p: A  x& e6 Z% S8 e职位要求3 I0 P. S3 V: [. }4 _  j
  0 q! u- {' B+ q; s" B0 P
射频大信号集成电路研发经验,熟悉半导体(Si,GaAs,GeSi等)工艺制程;  # ^) a+ C$ t9 f) w8 _
相关知识背景:微波射频/电磁场、模拟电路、信号与系统、通信系统;  3 R7 s, C1 K; S
熟练应用常用设计软件(ADS,Cadence)及常用测试设备(VNA,SA):非常看重射频实验室动手能力,射频测试中分析和解决问题的能力;  % G9 R1 ]3 L! s: _5 e6 f5 N
熟悉射频发射机前端架构,了解各模块指标要求,若对前端架构有独到见解,加分;  
# C8 s7 ~' e9 a5 R  n. V0 O9 T3 S若有CMOS/SiGe/SOI PA设计经验、新结构PA设计经验,加分;  6 |' n( j( b% i5 E8 i7 b: _
若有高效率PA、高线性PA设计经验,严重加分;  
6 l  a, _# D+ \( @) q若有关于多模多频段(MMMB)PA的新结构、新想法,严重加分;  0 F9 Q- z! P( e- p3 @
若有RF MEMS、Tunable Impedance Matching、先进封装技术等相关经验,严重加分。
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19#
發表於 2013-12-17 10:08:37 | 顯示全部樓層
无源器件/结构设计工程师
+ i. q! B- z% l( Y6 t; `; w1 U公      司:a fabless semiconductor company7 g" @! h% g5 l$ V$ D2 w# @' j
工作地点:北京4 ?6 g8 {& L* l3 t* H
$ \4 l, b  D4 N- R3 U/ ]
职位描述:RF PA及Switch产品中所需无源器件/结构设计  3 P3 ]) |+ d3 a. R: S% m0 o  q# V  r

$ k: d# H: d7 o2 E! a, j4 O微波/电磁场知识背景;  
1 T- z/ ]& l6 N" q# Y射频无源器件/结构设计经验,包含但不限于:集成平面/立体电感、电容、耦合器、Transformer、Hybrid、功率分配/合成结构等;  
* X3 A' V) U3 L& ~了解LNA、PA、Switch等射频电路的工作原理;  
- I/ X4 E) g$ n& _7 n) o熟悉常用设计软件(ADS,Cadence)及常用测试设备(VNA,SA);  ! s. B7 Z* w7 @" U) n7 L
若有SAW、BAW、FBAR滤波器的开发经验,加分;  
/ U! \5 y4 h3 {9 d/ y若擅于专利分析、专利申请撰写并熟悉专利事务流程,严重加分。
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20#
發表於 2014-2-11 14:50:49 | 顯示全部樓層
staff system engineer
( t% i2 y6 F9 d+ ^% N公      司:A famous IC company
2 Z) Y% P; ?4 Y0 c" ^* V/ c工作地点:上海7 F8 x5 y; C# a! v) X4 _

+ Q' z' a* a( ]9 w: PJob Description:   ~1 {5 K1 O5 N" t4 j8 T
The platform engineer at ***will be responsible for systems DVT (design verification test) and HW design for advanced RF/Mixed signal SOC products. The work includes test planning, automatic test (ATE) development, systems DVT, FPGA verification, SW regression testing and HW designs. The platform engineer will be working closely with a world-class team of Systems engineers, RFIC designers, ASIC engineers, SW engineers and marketing personnel.. As a platform Engineer within the team you will be contributing to the development/test of world leading tuner/mixed signal chips in a dynamic, fast-paced, and growing environment. The preferred applicant needs to have extensive knowledge of RF receiver/transmitter and demodulator in system design, verification and applications.9 t& Q3 E0 h$ S$ }

* `8 g4 `0 V8 M; T2 [; RRequired Skills:
' ?2 }7 O* e- J/ W·         Systems HW design and verification test experience in one or more of the following areas: analog/RF; digital SOC test; FPGA., W7 a8 F0 v( G8 I0 y2 I
·         RF/Mixed signal IC bring-up, trouble-shoot, test and characterization experience ! o; B& w# M, E, m8 d  _0 Y
·         PCB design skills (schematic design and extensive layout knowledge for RF/mixed signal ICs) 9 o, H: J' Z, C  O) N
·         Soldering skills and HW design prototype/debug skills
& |1 I: d; [) |! R, `5 ]  ]8 Q·         SW programming skills of Visual Basic and LabView or equivalent are required.
8 F5 B0 P* m% \! `·         Strong lab test skills with typical test equipment like network analyzer, Oscilloscope, signal generators, and spectrum analyzers0 C2 @4 ?* v5 S' ]4 [% s
·         FPGA verification experience is highly desired
& {" N  U# A! X3 A* A$ ^·         RF system block-level testing (LNA, Mixer, VCO, PLL, etc) experience is highly desired
8 u1 R9 t. F6 ]+ Z- |1 S1 Z·         Experience with documentation (Test report, test procedures, application notes) Good written and spoken English communication skills are necessary; g  J( p9 `& S
·         Good spoken and written English communication skills
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