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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-12-26 10:14:11 | 顯示全部樓層
Field Applications Engineer
6 m* I9 L1 Y8 x* X+ ~4 w! B+ Z4 l- Q公      司:A famous IC company
+ K& b2 G/ C. p工作地点:深圳
, `* I0 u+ u' D0 f
' F$ Q5 |9 t& R0 W; pJob Description / r. k  n% N) {( _/ W* v. m
Lead and manage a team of talented FAEs in supporting customer projects.  
+ J" |8 L4 G, \7 \& c8 t- `Design or modify PCB reference design to implement preferred RF & BB IC layouts.  
. o0 Z% b) A4 O9 H3 ?Work with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers. ' l7 r/ C$ N9 q! Q  T6 u- N& a
Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies. 2 R$ S1 u4 ^6 ]: f# a
Write appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs. / @( F% f, B, [
Work with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs.
! Y& Y  K1 g4 fWork with the Sales and Marketing Teams to promote the company’s products and technology advantages.
- J% S6 _) {5 g8 f# |8 h9 mWork with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  
6 ^7 J4 ]3 V2 M4 a4 LWork with customers to bring programs from concept stage through to production.  1 C% t0 ~+ O& W* b/ g; H
Work with customers and the internal Quality team to identify, debug and troubleshoot product quality issues./ S5 T2 r% n; i8 o* t# A3 b1 \" P

2 f- I7 k' n; H' p8 E, ~9 l# RRequired Experience  # c( b; Y! i- P
BS or MS in Electronics Engineering.  
  ]- i$ Q) X* _6 Q4 ]: zMinimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering 9 E: @6 ?% ^/ D" P6 y9 k
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. ) y8 {# j8 ]3 K3 ?. u& g
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
4 N9 W/ V. Y, dExperience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support.
2 C; B( d! C6 ~& g5 u* |This individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems.
' F4 r: `( u+ b* a7 QDecent English communication skills in both oral and written.
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2#
發表於 2013-12-26 10:15:05 | 顯示全部樓層
Sr Analog Designer
( D% J8 r+ g+ C1 F公      司:A leader in high performance analog and mixed-signal IC design& y" v' }! E% p, b
工作地点:北京' C$ `, G8 i- L8 C" I! {/ e7 d( i
! b" T7 \; _7 V1 m. X  f
Education and experience requirement / l3 J2 L" m2 I) o- {; o* C
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience 0 X& |. ]+ w* M8 K0 ]: a
o     Hands-on CMOS product design experience in two or more of the following areas
+ q5 P1 z* W9 w2 jo       Receiver front end, including analog front-end, demodulation, channel selection etc.
' ?& X: H! X, a& @' a% eo       High-precision ADC, including sigma-delta, pipeline etc
! k0 R8 {7 k7 p# ~1 ^9 Io       High-precision DAC
5 v' S' t5 I5 K  mo       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
2 \+ H/ z* w4 ~* d; Z+ d2 Do       High-precision oscillator/PLL/DLL ' W% \% N2 o. t8 }1 |& N' ]
o       Low noise voltage reference
8 Q6 a$ z5 k* Uo       On-chip high-voltage charge pump ( }, J) C* h0 D, t5 c. g/ c
?      Experience in system level definition, modeling and verification a plus 7 B( K' ]- w4 n! Z5 ~" ?3 u  k
?      Hands-on experience supervising layout and post-layout verification
- @! c7 O- z5 {, d! z0 s$ B0 G?      Proficiency in tools 1 m4 ]0 i9 F8 H) C$ N& s
o       Cadence design environment
* x1 Y/ A; J. u* [o       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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3#
發表於 2013-12-26 10:15:56 | 顯示全部樓層
Sr Analog Designer% |& @$ {! q: N) |+ W$ c9 G. z
公      司:A leader in high performance analog and mixed-signal IC design3 K  z/ g0 b6 Y) G0 e1 h5 s& y* @
工作地点:北京$ g! ^1 X( P* P& I7 G5 F/ p

0 J! W3 F+ E  M% t/ QEducation and experience requirement 2 U4 E! o; c% V- W: F0 H& G
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience * }3 x# X  D: m1 c
      Hands-on CMOS product design experience in two or more of the following areas ) R3 f. p; ^# r# I+ {
       Receiver front end, including analog front-end, demodulation, channel selection etc.
. t1 F* o& l/ Z4 |  L" l" I% P: k       High-precision ADC, including sigma-delta, pipeline etc ! d- |" S1 H9 e7 U( w% G: t8 D+ e
       High-precision DAC 1 z0 q/ b7 ]2 H9 `2 D
       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
% s4 Q6 ^7 K1 E6 c       High-precision oscillator/PLL/DLL . x+ ~0 `5 F2 n" j$ X( T5 Y
       Low noise voltage reference ) g4 j- k9 n- t: M
       On-chip high-voltage charge pump " C. o/ H( I$ w+ d) e
      Experience in system level definition, modeling and verification a plus
3 ~$ |2 X5 b% l4 C      Hands-on experience supervising layout and post-layout verification
! d7 i* M0 d7 a. r- A      Proficiency in tools 6 i" e8 r/ r/ M: t1 K# c
       Cadence design environment 6 n2 d0 r( B1 {6 ~
       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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