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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-12-26 10:14:11 | 顯示全部樓層
Field Applications Engineer, B1 Y0 r! p$ B+ {# v- t
公      司:A famous IC company. r. n- i/ r/ p( w  j1 W% f! N
工作地点:深圳$ T6 S8 u# _8 U  ?7 S" v. F. Q
! T+ Q) ^# i" L/ O1 Y: p- R
Job Description " C- ~) |$ A. L, e' Z" n
Lead and manage a team of talented FAEs in supporting customer projects.  7 a$ O4 a& ]+ Z) ?% f1 Z
Design or modify PCB reference design to implement preferred RF & BB IC layouts.  
2 N7 O! W: I- s5 r6 I6 qWork with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers.
+ t& A: t2 R0 j2 }Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies.
, U4 j' M1 O, l, N2 LWrite appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs. 0 V4 i2 |. p, g
Work with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs.
  l5 {7 ^; [6 F" S0 F2 s0 I; S( bWork with the Sales and Marketing Teams to promote the company’s products and technology advantages. 0 ?4 r/ M8 {4 d
Work with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  8 [7 W4 H$ [9 u
Work with customers to bring programs from concept stage through to production.  
! t+ {. w0 m) l& s$ nWork with customers and the internal Quality team to identify, debug and troubleshoot product quality issues.
' c! a, e3 A8 V+ i" |1 P2 D: N7 i. O
Required Experience  3 x: V! z2 y# m8 q1 ^0 D, _
BS or MS in Electronics Engineering.  
  [* d" M6 W* h$ ?6 iMinimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering
9 M- L3 n8 t; }5 V5 E$ A6 OThis individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. : f( W7 F. b2 P
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. 7 e0 M  }. E3 m4 J: W
Experience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support. 6 i$ E# j" w! C  X& o1 T5 J% o9 ?7 ?
This individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems.
: H5 A/ V' z0 R& o6 s* V. f, SDecent English communication skills in both oral and written.
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2#
發表於 2013-12-26 10:15:05 | 顯示全部樓層
Sr Analog Designer$ s7 d# f5 C/ r8 T: \- G7 U$ `9 R
公      司:A leader in high performance analog and mixed-signal IC design% U! f$ j3 f( O" T6 H- i
工作地点:北京1 l( X% B( x! ^# i8 [# ?, I# O

' U; S0 V. I& K; dEducation and experience requirement 8 l+ n, x9 {. w) h
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience , k# U' @8 F5 N! S; {, {. x2 l
o     Hands-on CMOS product design experience in two or more of the following areas 3 d7 j. C/ M! z8 D
o       Receiver front end, including analog front-end, demodulation, channel selection etc. & P5 v2 ?$ c' r0 N5 {2 z( P
o       High-precision ADC, including sigma-delta, pipeline etc : q& |' y$ x0 k* J1 w% B  e
o       High-precision DAC
( x  v5 |7 O% g! T; A3 X- K6 ?o       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design + K! v0 Z$ t9 h* R
o       High-precision oscillator/PLL/DLL 7 j5 _5 j6 E7 ?+ @  {3 {- O% h
o       Low noise voltage reference
( k( d+ ~3 r/ o, V5 a: ^* f2 no       On-chip high-voltage charge pump ) K% g& d  ^6 E, V
?      Experience in system level definition, modeling and verification a plus 2 j: }; L6 W4 I! r* w
?      Hands-on experience supervising layout and post-layout verification ( c" \* E: R5 }) M
?      Proficiency in tools
* k3 A1 r- G( O/ W7 X6 Xo       Cadence design environment 3 Z6 i. }( O# W, T" Y  S3 j  g* K
o       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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3#
發表於 2013-12-26 10:15:56 | 顯示全部樓層
Sr Analog Designer, z3 J7 F( c8 G& Q. p
公      司:A leader in high performance analog and mixed-signal IC design
7 z& l  Q% m* \3 J工作地点:北京
+ q6 w" q2 c- Z* J. N' ^4 Z# p2 p' v
Education and experience requirement ; L2 k4 q& B- d0 ~0 R2 N
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience / g$ v5 c1 z5 w2 i
      Hands-on CMOS product design experience in two or more of the following areas 0 Z% E' T' i* @0 h# C
       Receiver front end, including analog front-end, demodulation, channel selection etc. : Y1 c2 p' I7 t1 W
       High-precision ADC, including sigma-delta, pipeline etc   h; r0 C9 b( N& Z6 |' C9 N" b$ N, M
       High-precision DAC
& q$ L0 w+ ]0 i; f       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
0 e$ `3 F( `: ?       High-precision oscillator/PLL/DLL
  w0 o' L2 J6 E) A. X( L- k       Low noise voltage reference ; {6 w4 a, t8 _' E( v3 ?: ]
       On-chip high-voltage charge pump ) F0 \0 b1 U9 |5 V3 \8 Z; l5 {8 r
      Experience in system level definition, modeling and verification a plus
$ [' l0 r- ^! R# z% j; E      Hands-on experience supervising layout and post-layout verification ( s7 w4 {8 Y; O& \) E$ ?
      Proficiency in tools
1 o6 S2 ]9 C1 O) E! Q% T2 R       Cadence design environment
3 F9 O( Q# f& U       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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