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[問題求助] VHDL PS/2 Keyboard 程式問題..thx

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發表於 2008-1-23 17:29:22 | 顯示全部樓層 |閱讀模式
目前需要使用MAXII 1270 做PS/2 Keyboard控制,在網路上找到了用VHDL寫PS/2介面,經過測試後正常,但輸出是8個Pin輸出(並聯),但我希望輸出為1個Pin(串聯)輸出,請問我該如果修改程式呢?請大家幫幫忙,給個意見,或者提供任何資料參考...thx
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程式如下:. F4 W: @$ D1 P# n, Q# l
-- PS2_Ctrl.vhd  [, ]; m" Q) F/ B
-- ------------------------------------------------& ?- C( V; i* a. \* E$ k6 D
-- Simplified PS/2 Controller (kbd, mouse...)
( h5 I' C- y$ X& d/ C1 k-- ------------------------------------------------
1 B7 V! |; ^- |! Z0 N-- Only the Receive function is implemented !  _( Q9 u; s! C0 T
-- (c) ALSE. http://www.alse-fr.com
0 h8 B+ J; ~, @  [library IEEE;
% a% j+ c! `6 ~7 ?use IEEE.STD_LOGIC_1164.all;3 i- h+ d* Z. o- Y) O: c! F
use IEEE.Numeric_std.all;
4 n8 J: U* _8 Y-- --------------------------------------$ n2 e0 Q. \0 O
Entity PS2_Ctrl is" D- Q# k8 R; z* _
-- --------------------------------------
  D% h3 u6 N$ X8 y+ Cgeneric (FilterSize : positive := 8);
4 ?# ^7 Q& e$ h# I$ Rport( Clk : in std_logic; -- System Clock4 q# B1 S$ i3 h$ K- ]
Reset : in std_logic; -- System Reset
3 C$ J; l2 g5 ?3 s( qPS2_Clk : in std_logic; -- Keyboard Clock Line
. H; C% G: s. c, s6 CPS2_Data : in std_logic; -- Keyboard Data Line2 b+ ?) I( K* |+ z" O% j0 y
DoRead : in std_logic; -- From outside when reading the scan code1 ?* ?6 k& N9 G, L- N- L
Scan_Err : out std_logic; -- To outside : Parity or Overflow error5 o) N% N) A( M- N
Scan_DAV : out std_logic; -- To outside when a scan code has arrived7 m# S+ s7 P/ s- N
Scan_Code : out std_logic_vector(7 downto 0) -- Eight bits Data Out
) f, ~* e1 l" }6 X8 ~# H% ?);$ F3 V. g8 y$ n7 X& e% G$ g
end PS2_Ctrl;
, X" F# v9 R- i6 }' L-- --------------------------------------
6 h4 j0 h5 g- QArchitecture ALSE_RTL of PS2_Ctrl is5 D; P8 k( m+ W8 t
-- --------------------------------------9 ^4 J3 J# G) q& z3 {
-- (c) ALSE. http://www.alse-fr.com
& t2 N$ L' O( j' Z4 z  p# N" N-- Author : Bert Cuzeau.
$ K3 E: [# c, l4 O/ v& Q-- Fully synchronous solution, same Filter on PS2_Clk.0 Q1 ^2 F4 x. ~  l, \" H- D
-- Still as compact as "Plain_wrong"...# W, S( P- f9 y+ |4 n
-- Possible improvement : add TIMEOUT on PS2_Clk while shifting
" b- {+ D( N+ f$ a/ y-- Note: PS2_Data is resynchronized though this should not be# i4 ^" `0 P! u) w" H/ ?2 I6 ^
-- necessary (qualified by Fall_Clk and does not change at that time).
3 }+ i. g3 [8 C9 |: x-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation.
9 O6 r# Q0 T  N. N3 D/ psignal PS2_Datr : std_logic;, q7 j' G/ S! Y/ Q* Q! I
subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);
! Z2 m' g0 q0 Y! D; n7 ^signal Filter : Filter_t;& C, s- {4 o8 t: G+ ]9 |; {
signal Fall_Clk : std_logic;
0 j1 E6 b2 U+ |5 y; M) M: f3 Esignal Bit_Cnt : unsigned (3 downto 0);0 M* j1 O/ p1 @1 `" e( ?1 a
signal Parity : std_logic;/ T* U7 \9 O) P1 h% @+ B
signal Scan_DAVi : std_logic;
8 I. Q  Z- }" R3 K# P! Qsignal S_Reg : std_logic_vector(8 downto 0);6 @! u1 w$ w+ w! q
signal PS2_Clk_f : std_logic;
( H$ w  `( D2 J2 J2 o3 @Type State_t is (Idle, Shifting);
4 y) F6 m1 o  g/ Y* [signal State : State_t;
* n! J2 }0 ?% f7 ]9 Cbegin% h5 ?: E" V3 q) R& A4 V
Scan_DAV <= Scan_DAVi;
6 q. M, y! M# ]' b  N3 E$ c; Y7 E-- This filters digitally the raw clock signal coming from the keyboard :
0 v: r, M$ ^4 c0 r$ y8 y% P-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high2 D7 k* O8 e4 T8 d
-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low8 I% f* ?, M1 y& {1 G; a' ?5 e& x
-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data8 @/ Z5 _; o. v% R8 c' G7 W. ?. Z7 n
-- Also in charge of the re-synchronization of PS2_Data$ p% e7 n8 B5 `4 S
process (Clk,Reset)# @+ _8 O  j. Y5 y0 N4 i1 \
begin
5 ]8 @6 x" L  eif Reset='0' then
# n" C  O& V: [) A8 v, K/ V, ]PS2_Datr <= '0';
& ?6 r1 ]8 F; W8 c2 aPS2_Clk_f <= '0';
; J, N" X9 U  FFilter <= (others=>'0');
( m3 j. S+ S, y/ ~Fall_Clk <= '0';4 p4 T0 W) m; f+ a5 v
elsif rising_edge (Clk) then0 q9 n% w0 ^" x- `2 }$ H
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
6 l4 E' s5 i5 r% F9 `Fall_Clk <= '0';  C+ e; A; y' y9 b" Q- S0 D6 R; s7 X
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
+ q6 @; }6 r# n' Kif Filter = Filter_t'(others=>'1') then
0 ?. N7 M# w, |; t' J/ i( W, YPS2_Clk_f <= '1';, A3 O9 A; x0 }# N& E# a
elsif Filter = Filter_t'(others=>'0') then
: C6 l6 I5 N9 o, OPS2_Clk_f <= '0';- @! d: B; f' g# t: p/ m/ i1 Z
if PS2_Clk_f = '1' then
5 b0 U1 C# F% l4 j$ V7 aFall_Clk <= '1';  G9 R+ Z  M6 P3 J. a- i) K! H3 X
end if;) g0 T; y' |% o) h! R
end if;' z6 l6 S2 X2 ]8 j$ s& I) t
end if;
5 G) e( X- ^; L1 R% R1 Tend process;, W& F& @8 t) @1 S% k1 g
-- This simple State Machine reads in the Serial Data
+ E4 W5 K' X; f7 q% V5 L% \! g-- coming from the PS/2 peripheral.
& I# D  S. m* x+ }5 X3 |process(Clk,Reset)
7 a3 t; s9 I- e$ W0 m+ n6 Jbegin
" F. d+ p8 v. E8 _! m) A2 Q4 Y3 l) Jif Reset='0' then
1 K# G# V6 z! a; z6 b2 T$ Z6 X. F; R4 SState <= Idle;" L0 [& E9 N6 G7 U6 m
Bit_Cnt <= (others => '0');
7 |  Y5 u2 S# J+ o1 aS_Reg <= (others => '0');1 d' ^* l  b- n! Y& g
Scan_Code <= (others => '0');
2 m) }$ u* c& ~& ]Parity <= '0';5 A$ U3 o2 P5 A
Scan_Davi <= '0';  {+ }8 N6 J9 b8 @; k: M
Scan_Err <= '0';
! j6 W3 B3 B: f) f$ nelsif rising_edge (Clk) then
4 c) R! c. I; W: S/ o! eif DoRead='1' then
. X* ?$ y3 M7 Z* I" m# D: w2 q2 g# SScan_Davi <= '0'; -- note: this assgnmnt can be overriden
4 \7 g5 V6 i- c: w1 q) ^" Vend if;3 v7 E' G7 y* G2 T3 _  O. W
case State is. ~  T, @- N& ]( b- D3 _( p$ p! J$ ?
when Idle =>
0 a6 U+ Q) M& O7 c) ~. RParity <= '0';
! Y- q: }  |) ?4 w) ^Bit_Cnt <= (others => '0');3 y$ s/ G' J  j; L" w$ d' w
-- note that we dont need to clear the Shift Register; F  [+ }5 d  i' Y
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit- N8 K$ z# y1 \6 G" D
Scan_Err <= '0';
* K; V* `- [9 w. \; \2 PState <= Shifting;1 _8 k# {2 s# Q( w+ L
end if;
4 G* b- ?3 @2 K6 }) \% c# Q( ^when Shifting =>4 j1 W2 c1 j0 V- @$ E4 U
if Bit_Cnt >= 9 then
1 {- S" @5 p- [0 n( rif Fall_Clk='1' then -- Stop Bit
' S4 J+ z, ~' L  x' f1 J-- Error is (wrong Parity) or (Stop='0') or Overflow
% m. C" b$ k9 ?4 ~7 EScan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi;
5 R5 F. D1 t( H1 L) `/ aScan_Davi <= '1';, `5 k9 U, D' B4 r5 K
Scan_Code <= S_Reg(7 downto 0);
& q3 {6 O3 ~% k: W1 SState <= Idle;
3 D% o+ ]& E$ u2 C9 Qend if;( _6 H. k6 e5 S$ h
elsif Fall_Clk='1' then; N8 `: |; K- [2 ~9 c4 I
Bit_Cnt <= Bit_Cnt + 1;. E( O- O  D  }4 Q" x$ g; b8 X
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right$ y  U. E! j( J! N( r5 C
Parity <= Parity xor PS2_Datr;/ {3 G9 p7 g4 ~
end if;' X8 b) q) ?1 W
when others => -- never reached
  |, }, `& w$ U2 S3 ?State <= Idle;' K! ]7 q( T' g
end case;
' y( w' v( D( w! e4 W" N: }% x+ s, M& o- xend if;# z6 E/ h4 d; \" e( ]
end process;+ C, j) O' V$ V- [. ~! E
end ALSE_RTL;
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