|
4#
樓主 |
發表於 2013-12-12 09:14:21
|
只看該作者
Senior Physical Design Engineer
) A: @# W' h l* ~: P$ ]公 司:A famous IC company
: ?* j3 E0 J2 H- u2 i O; B工作地点:南京. [3 N( Z8 |9 G/ w0 c3 \) n7 ]; F$ C% p
/ Q* P' p% c- x8 l/ ~' N7 }
Key Responsibilities
. e) K2 J1 u0 E9 t( `: wDepending on experience, key responsibilities will involve some of the following:
: w$ |6 s8 N6 V" M$ I6 @7 I/ oIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. 0 v$ o' M" w* f
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
4 _! [ ^+ O* Y4 m! ULeading a team of physical design engineers and resolving the technical related issues.
: l9 J3 M7 p. {& W+ m% E WCrosstalk analysis, power analysis, and static timing analysis. 7 F2 `) ^; z( t( k: t
Write scripts in Tcl to improve productivity. 8 \, p+ m3 [5 I7 `
; _5 U! [! T3 T2 q/ |/ r职位要求
* I! ^! c& P1 Q* U4 kExperience: 5+ years in physical implementation engineering ( e" F9 \; J, x: `5 Q
Essential skills 5 [% D. |* P6 I6 g' m5 q1 x
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills ' }" d: a# }) l
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
+ w8 O3 X, C* U, ?; PGood programming skill. Capable of writing Tcl or Perl. 3 W/ t s" n' {7 ` {; h
Familiar with synthesis, static timing analysis. 5 C& Q. E' }1 i* V7 V0 t X0 S
Self-motivated team worker, good verbal and written communication skills in English.
2 D! R" F6 Z# I* ^2 ]Technical and team leadership proffered. Previous management experience highly desired.
* @. ^+ r. r0 M- gExperience with synthesis, DFT, and verification is preferred. |
|