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Senior Physical Design Engineer
7 Y) u& b& Q) r6 I! d公 司:A famous IC company, I3 L+ p* f, L- a Z4 H/ G+ b
工作地点:南京8 E5 a2 P+ U1 q" }
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Key Responsibilities ; Y6 ~6 _5 S$ J/ h7 h7 X$ u0 l* i
Depending on experience, key responsibilities will involve some of the following: 6 N; b' P$ E6 x$ ^
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. 6 t! V2 f/ t( c0 d
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed. ) A% C; H6 f( W w4 w) n# W
Leading a team of physical design engineers and resolving the technical related issues.
; m# e2 z! ?& B- m7 R6 KCrosstalk analysis, power analysis, and static timing analysis. * B: o5 d6 F5 [; J# N1 Z( m) S2 ^2 l. I
Write scripts in Tcl to improve productivity. 0 F& f0 {# ^: w O( b
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Experience: 5+ years in physical implementation engineering
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Essential skills
- e9 x9 f+ r% sMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills ; }% `9 O/ R8 W/ p
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
. W' S& R F+ F, kGood programming skill. Capable of writing Tcl or Perl.
3 O: L% n8 C1 Y7 @% iFamiliar with synthesis, static timing analysis.
/ Z! `: r/ V# A4 ?: I$ I* K7 jSelf-motivated team worker, good verbal and written communication skills in English.
% J/ k2 j$ l1 c/ BTechnical and team leadership proffered. Previous management experience highly desired. # t* }6 ]; ]6 H$ n; t: _
Experience with synthesis, DFT, and verification is preferred. |
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