For Circuit Simulation on your current project

sophiew · 發表於 2013-9-3 16:25:23

In your verification flow, please select the primary EDA vendor/tool your team is using...

If other (please specify), or you don’t know?

ranica · 發表於 2013-11-26 09:19:31

EE (Electrical & Signal)

公    司：an international group of companies
工作地点：上海

DUTIES AND RESPONSIBILITIES
·       Electrical design from concept through to production.
·       Analogue and Digital Electronic circuit design experience is essential.
·       Participate in or lead a large project entirely.
·       Able to manage designs and projects from requirements through to manufacture.
·       A good understanding of design for manufactures and test methodologies.

KNOWLEDGE, SKILLS, AND ABILITIES REQUIRED:
·       Bachelor degree, relevant major.
·       Must be able to work both independently and as part of a team.
·       Minimum 5 years’ experience in analogue and digital electrical circuit design for mid / high volume products.
·       Experience in communication with PCB manufacturing suppliers.
·       Must be pro-active and results driven
·       Experience in optical industry is a strong plus.

tk02376 · 發表於 2013-12-26 10:16:42

Telephony performance Engineer
公    司：A famous IC company
工作地点：上海

Responsibilities:
*** is looking for a software engineer for telephony QA and performance optimization. It will be responsible for XX telephony stack quality assurance, including design/patch review, test case/tool development, performance analysis/optimization, customer issue analysis and others. This position needs a good technical/programming and quick learning capability to handle the task in design/code review, issue analysis etc.

Qualifications:
1)    Typically requires a BS (CS or EE) degree and 5 years of experience or an MS (CS or EE) degree and 3 years experience
2)    Experience with telephony service, 3GPP protocol, AP/CP communication development/validation is preferred.
3)    Experience in C/C++/JAVA programming is required.
4)    Experience in Linux/Android shell/tools development is desirable
5)    Telephony related Performance analysis experience is desirable.
6)    Good in communication and team work.

amatom · 發表於 2014-1-10 11:03:13

模拟IC设计人员
公司：a fabless semiconductor company
工作地点：上海

职位描述：
1. 根据双界面卡系统应用或市场要求，确定模拟电路的需求定义和设计描述。
2. 根据系统要求, 选择适当的模拟电路和整体框架，并对模拟模块的集成做出规划（包括14443 AFE、电源管理、LDO、ROSC、POR、 I/O，ESD等）。
4. 设计/改进模拟电路（包括14443 AFE、 PMU、ROSC、PRO、TD等），满足设定参数，并保证芯片生产的良率要求。
5. 配合版图工程师完成电路的版图制作，评估版图对电路性能的影响并改良。
6. 有14443 AFE和PMU模拟电路设计经验的优先考虑。

amatom · 發表於 2014-1-10 11:04:28

Hardware Applications Engineer–Graphics
公司：A famous IC company
工作地点：上海

Job Requirements：
Desirable Strong understanding of microprocessors
A good understanding of the interaction between software and hardware
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
C/C++, assembler coding or other programming skills.
Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

Education
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.

amatom · 發表於 2014-1-10 11:04:32

Experience
Minimum of 4 years industrial experience
Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
Experience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
Professional experience of customer and sales interaction
Demonstrable experience of problem solving and debug skills

Personal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
Must be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
Must be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.
Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
Must be willing to be flexible and accept new challenges
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons

ranica · 發表於 2014-1-13 15:25:00

Senior Audio Software Engineer
公    司：A famous IC company
工作地点：北京

Job Description:
1.       Develop embedded Audio subsystem for XX HW platform.
2.       Optimizing and porting the audio codes, framework and software solutions.
3.       Customization, deployment and maintenance of distribution on our hardware platforms
4.       Improve and maintain existing software components
5.       Assist with the hardware design and performance evaluation.

Qualifications:
1.       With 3+ years of relevant working experience
2.       Excellent algorithm background about common DSP and multimedia functions/applications
3.       Solid knowledge/experience on the C/C++ and Assembly programming languages
4.       Excellent understanding of the embedded system architecture, familiar with the embedded OS Linux, RTOS.
5.       Excellent hands-on skill on software programming, optimization, testing and debugging
6.       Experience on audio codec such as MP3, AAC, WMA, Dolby AC3...
7.       Experience on audio post-processing such as downmixing, resample-rate...
8.       Excellent fixed-point programming.

ranica · 發表於 2014-1-13 15:25:34

Analog Design Engineer/Lead
公    司：A microelectronics company
工作地点：深圳

Responsibility:
1.Responsible for analog IC designs, simulations, verifications and layout supervisions.
2. Establish the analog design methodology to ensure quality and IP reuse.
3.Discrete IC definition, IP integration, implementation and project coordination.

Requirements:
1. MS/Ph.D. in Electrical Engineering
2. At least 5+ years of experience in analog IC Designs.
3. Familiar with PLL, ADC, DAC, OP, Class D, Power Manager IC.
4. Familiarity with laboratory equipment (oscilloscope, spectrum analyzer..) is a must.
5. Good team work spirit, easy to cooperate with team members.

ranica · 發表於 2014-2-18 08:46:10

龙旗高薪诚聘研发工程师
地区：上海、惠州、深圳

岗位类别：驱动工程师、MMI（android）应用工程师、射频工程师、基带工程师、结构工程师、Layout工程师、项目经理
岗位级别：一般或高级以上
数量需求：不限

JD：
1、基带工程师
工作职责：
1、按时、按质完成项目的研发计划：为了确保基带各模块正常工作，能够按时完成原理图制作，摆件，调试，解决存在问题，达到公司规定的标准；
2、基带技术的研发和调试,文档拟制：为了确保基带技术研发的功能，性能，质量和进度，使基带技术的研发符合产品定义书的要求，完成具体基带技术的研发，协调与其它部门或合作者的接口技术与关系。在公司制度与流程规定的范围内，完成基带技术文档的拟制；
3、基带技术的关键节点评审：为了实现部门和项目的正常运作，在公司制度与流程规定的范围内，参加基带技术的关键节点的评审；
4、项目问题的解决：负责指导对项目中的具体问题的解决，并提供修改方案，参与评估导入的解决对策，总结项目出现的问题，积累技术；
5、其他部门所需要的基带技术支持：为了实现部门与项目的正常运作，在公司制度与流程规定的范围内，在基带技术方面支持其他部门的工作。
任职要求：
1、学历：本科及以上学历；
2、专业：通信、电子等相关专业；
3、工作经验：了解通信原理，一般工程师有1年以上的手机基带开发经验，高级工程师有3年以上的手机基带开发经验，熟悉整个项目流程，具有一定项目工作经验，可以独立设计调试整个基带。熟悉硬件各种测试设备，了解公司及其国家测试标准；
4、其他：掌握各种数字电路和模拟电路知识，具有较强的嵌入式系统的开发技能和实际经验；熟悉移动通信的基本原理和相关知识；具创新精神及团队合作精神。

ranica · 發表於 2014-2-18 08:46:27

2、驱动工程师
主要工作职责：
1、Android的bsp的驱动工程师，linux系统维护；
2、智能手机驱动调试和维护，新的器件调试；
3、中间件开发。

任职要求：
1、本科以上学历，软件相关专业；
2、有1年以上基于手机 Android系统的驱动开发经验，精通 Android 驱动体系架构；
3、工作主动，有良好的团队精神和敬业精神。

3、射频工程师
工作职责：
1、按时、按质完成项目的研发计划：按时完成原理图制作，摆件，调试，解决存在问题，达到公司规定的标准；
2、射频技术的研发和调试,文档拟制：确保射频技术研发的功能，性能，质量和进度，使射频技术的研发符合产品定义书的要求，完成具体射频技术的研发，协调与其它部门或合作者的接口技术与关系，完成射频技术文档的填写及归档；
3、射频技术关键节点的跟踪和问题解决：参加射频技术关键节点的跟踪。负责指导对项目中具体问题的解决，并提供修改方案，参与评估导入的解决对策，总结项目出现的问题，积累技术；
4、其他部门所需要的射频技术支持；
5、跟踪新器件或功能的使用：确保手机所用新的器件能够按时、按质设计到手机硬件，不影响项目开发的周期，评估新模块的接口，与手机系统的匹配，及时与厂商合作，完成新的设计或替换工作；
6、新技术新平台可行性验证：确保新技术的引入和重要项目的成功启动，参与对新技术新平台的可行性验证。

任职要求：
1、学历：本科及以上学历；
2、专业：通信、电子、微波等相关专业；
3、工作经验：了解通信原理，有1年以上的手机射频开发经验，高级工程师有3年以上的手机射频开发经验，熟悉整个项目流程，具有一定项目工作经验，可以独立设计调试整个射频；
4、其他：掌握各种数字电路和模拟电路知识，熟悉移动通信的基本原理和相关知识；具有创新精神及团队合作精神；
5、有MTK和展讯平台射频开发经验者优先。

sophiew · 發表於 2014-5-23 09:55:38

Sr. Reliability Engineer
公    司：A global PC leading enterprise
工作地点：深圳

Position Description:
   Develop reliability test plan for the company MEMS product based on good understanding of properties critical for sensor performance, material characteristics and limitations, mechanisms of their degradation;
   Supervise reliability tests execution, analyze and report test results; facilitate accelerated development timelines;
   Perform failure analysis of the sensor as a whole and its components, materials, coatings to support design and process team in improving sensor performance;
   Job requires ability to plan, and consistently deliver against plan on development and release to production milestones.

Job responsibilities include:
   Work in team environment on developing test hardware and software;
   Lead reliability characterization of MEMS sensor and its internal components.
   Work on failure analysis projects to give feedback to internal process and packaging development teams.
   Deliver against the schedule and communicate status to various levels of management, peers and team members;
   Work in a team environment to determine and improve product and material related issues;
   Contribute to the design and architecture of future products

Education:
   MS or PhD in Material Science, Material Engineering, Chemistry, or Physics.

Qualifications:
   In depth understanding of properties and chemistry of organic (polymers) and inorganic materials/coatings; excellent knowledge of respective analytical methods, defectoscopy.
   Experience with semiconductor packaging, flip-chip technology, adhesives, metallic and semiconductor thin films.
   Proven record of successful analytical work related either to introduction of new products in the mass production, or supporting volume manufacturing;
   Good knowledge and understanding of JEDEC, ASTM reliability test standards
   Excellent verbal and written language skills (English).

Experience:
   10+ Years minimum industry experience in conducting reliability tests and failure analysis.
   Demonstrated track record of bringing microelectronic components to volume manufacturing.

sophiew · 發表於 2014-5-23 09:56:12

Device development engineer
公    司：A famous IC company
工作地点：上海

Duties
·       Facilitate product design work in foundry process(LG, MS and BCD process).
·       Have a strong device/process background for 90nm~0.18um logic process, mixed-signal, embedded FLASH memory, and BCD process.
·       Tasks would include answering device  and process related questions, interpreting DRC and LVS results, helping with tapeout and mask ordering, doing jobview mask inspections, and also participate the process/device development projects.
·       Would be expected to establish relationships with his technical peers at foundries and discuss important technical issues with them on an almost daily basis.

Requirements
·       Senior level engineer (minimum 8 years experience with BSEE or minimum 5 years experience with MSEE or PhD)
·       Excellent device knowledge (LV CMOS, BJT, BCD, embedded FLASH memory, OTP/MTP, latchup, ESD, device reliability)
·       Excellent to very good knowledge of PDK systems (design rule, verification software, mask ordering, device pcells, circuit modeling, parasitic parameter extraction, and so on)
·       Some knowledge of circuit design, primarily from a device usage standpoint.
·       Knowledge of major Asian foundry systems, process technologies, and devices would be a positive.
·       Ability to understand and solved technical problems relating to semiconductor devices with a minimal amount of guidance.
·       Excellent people/communication skills

sophiew · 發表於 2014-7-25 10:55:28

Job Title

& R Engineer
Job Category :Semiconductor
Location : Malaysia
Job Type : Permanent
Job Description:
Design house looking of experience DSM P&R engineers

Responsibilities:
Implement multimillion gate designs in cutting edge process technologies (28nm, 45nm & 65nm).
Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout.
Clear understanding and command over all aspects of physical design.
Proficient in timing closure multiple clock domains, IR drop analysis, physical verification, SI/PI, and design closure tasks of IP and/or SoC.
Work with RTL designers and IP owners to understand the design complexity and plan physical design activities.
Run equivalence checks across gates-to-gates as design progresses.

Requirements:
BSEE,MSEE preferred ,3+ years of experience in large VLSI physical design implementation.
Knowledge of Cadence Virtuoso/VirtuosoXL layout editor, Cadence SOC Encounter P & R tool,
Knowledge of Calibre DRC/LVS, Primetime, Star RC ,RF analog or mixed signal layout experience with CMOS, BiCMOS or Bipolar processes
Develop P&R scripts.
Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues. Successful track record of delivering products to production.

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