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sophiew

Sr. Reliability Engineer
* E- D# v2 \, }1 T6 n( h: H$ E公      司：A global PC leading enterprise
6 P) {, Y. X& G2 t% A5 _工作地点：深圳
# _6 s$ M& i0 ]( e/ w
Position Description:
       Develop reliability test plan for the company MEMS product based on good understanding of properties critical for sensor performance, material characteristics and limitations, mechanisms of their degradation;
) `" \# o) Z* o- I       Supervise reliability tests execution, analyze and report test results; facilitate accelerated development timelines;
3 @: ~% ~; P) J& \0 d7 w, q       Perform failure analysis of the sensor as a whole and its components, materials, coatings to support design and process team in improving sensor performance;
6 C2 c& ^5 R+ c% U       Job requires ability to plan, and consistently deliver against plan on development and release to production milestones.

Job responsibilities include:
       Work in team environment on developing test hardware and software;  
       Lead reliability characterization of MEMS sensor and its internal components.
" M2 W. L6 c- p) D8 k6 s       Work on failure analysis projects to give feedback to internal process and packaging development teams.
       Deliver against the schedule and communicate status to various levels of management, peers and team members;
: M& A' C/ ~+ X' t, J       Work in a team environment to determine and improve product and material related issues;
2 W1 R- z, L: j6 j       Contribute to the design and architecture of future products

Education:
       MS or PhD in Material Science, Material Engineering, Chemistry, or Physics.

+ ?4 m9 o% @6 a5 b; s4 J, x1 Z+ c/ tQualifications:
$ F/ a( B6 R4 t! B, U4 F       In depth understanding of properties and chemistry of organic (polymers) and inorganic materials/coatings; excellent knowledge of respective analytical methods, defectoscopy.
3 [0 \) O( x8 q% `& j       Experience with semiconductor packaging, flip-chip technology, adhesives, metallic and semiconductor thin films.
% M% x  p: F  }- ~, y       Proven record of successful analytical work related either to introduction of new products in the mass production, or supporting volume manufacturing;
       Good knowledge and understanding of JEDEC, ASTM reliability test standards
9 R, u- ~6 j! m( ^5 |- U9 {       Excellent verbal and written language skills (English).
' w1 @# J% Q! {5 p6 E( G1 c: B
1 E% s! j8 ?; V# DExperience:
$ O- J' c) V9 R! @1 z* s       10+ Years minimum industry experience in conducting reliability tests and failure analysis.
( {5 q* l! H7 E- m; A" p       Demonstrated track record of bringing microelectronic components to volume manufacturing.

sophiew

Device development engineer
  @9 U' ?/ m+ \, c8 C2 l8 O8 E/ i公      司：A famous IC company
% I- y$ ~0 u% ^8 A6 P9 Y1 x& r工作地点：上海

( G- Q( _* Z$ u- E! pDuties
·         Facilitate product design work in foundry process(LG, MS and BCD process).   
·         Have a strong device/process background for 90nm~0.18um logic process, mixed-signal, embedded FLASH memory, and BCD process.
·         Tasks would include answering device  and process related questions, interpreting DRC and LVS results, helping with tapeout and mask ordering, doing jobview mask inspections, and also participate the process/device development projects.
0 y& x7 E* j/ W/ q# {6 u·         Would be expected to establish relationships with his technical peers at foundries and discuss important technical issues with them on an almost daily basis.  
, j( Z# g( _) l& e% M
Requirements
·         Senior level engineer (minimum 8 years experience with BSEE or minimum 5 years experience with MSEE or PhD)
·         Excellent device knowledge (LV CMOS, BJT, BCD, embedded FLASH memory, OTP/MTP, latchup, ESD, device reliability)
·         Excellent to very good knowledge of PDK systems (design rule, verification software, mask ordering, device pcells, circuit modeling, parasitic parameter extraction, and so on)
; ^0 v& S' O. O·         Some knowledge of circuit design, primarily from a device usage standpoint.  
·         Knowledge of major Asian foundry systems, process technologies, and devices would be a positive.  
·         Ability to understand and solved technical problems relating to semiconductor devices with a minimal amount of guidance.
·         Excellent people/communication skills

sophiew

Job Title & R Engineer
# v2 e: N5 h3 r+ N  U2 qJob Category :Semiconductor
( K9 }* X" r1 H  ?3 c$ M. cLocation : Malaysia
  y8 w, D" W3 H& B2 UJob Type : Permanent
& \; x" h* M2 e5 i+ LJob Description:
. C5 x& @3 u3 R: d/ x' ZDesign house looking of experience DSM P&R engineers

Responsibilities:
3 h3 v# F: v; j2 b8 U8 C$ |Implement multimillion gate designs in cutting edge process technologies (28nm, 45nm & 65nm).
Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout.
Clear understanding and command over all aspects of physical design.
Proficient in timing closure multiple clock domains, IR drop analysis, physical verification, SI/PI, and design closure tasks of IP and/or SoC.
Work with RTL designers and IP owners to understand the design complexity and plan physical design activities.
; G+ [+ t' e7 gRun equivalence checks across gates-to-gates as design progresses.
: G5 \; U$ N$ ?5 O. ~6 L* r5 J: l
5 |3 o3 l* j/ N; tRequirements:
BSEE,MSEE preferred ,3+ years of experience in large VLSI physical design implementation.
& _. t/ a  F' }4 ~' F7 B: UKnowledge of Cadence Virtuoso/VirtuosoXL layout editor, Cadence SOC Encounter P & R tool,
8 `. A$ u6 Q% [4 [# |2 MKnowledge of Calibre DRC/LVS, Primetime, Star RC ,RF analog or mixed signal layout experience with CMOS, BiCMOS or Bipolar processes
7 I" i& s; z& j4 K% @$ D. \# h* V0 aDevelop P&R scripts.
Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues. Successful track record of delivering products to production.