|
發表於 2014-7-25 10:56:12
|
顯示全部樓層
Job Title igital verification Engineer
3 C! n1 [7 ^) bJob Category :Semiconductor5 q1 y: r. M! @) R# I9 _, [. Q! {! o
Location : Singapore: L: t5 t z% T$ j$ H; r$ r& }
Job Type : Permanent, v) q% t2 c0 _: Q* L' V
Job Description:
9 O! |4 u9 q$ k! W. wLooking for SoC Verification Engineers Experienced in System Verilog Tools; C5 o. ]; [5 y2 p- u% v( M- g
$ {3 @/ q9 k w9 K' ZResponsibilities:
/ k6 {$ s5 X" K6 b% F, _Constrained-Random Verification using SystemVerilog.
. C7 l# N& Z3 ?1 @Develop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.
4 m9 Q; e, O# x6 c9 yDevelop Bus Functional Model(BFM) or using Verification IP(VIP) for tests
) o( M+ f( k) R+ fDeveloping and reviewing test plans) g5 h# x, d5 ?. r$ i+ g# {
Write coverage monitors to evaluate the coverage of the DUT.: N: D$ o) D& K! T( g" T/ u0 e
Formal verification using SystemVerilog Assertion to verify SOC or IP is plus
1 s0 S7 g( Q1 _& Q% S6 d/ `, a3 h) s; g: ]1 N( M, X8 {" L
Requirements:% A a9 w K- U: `
>4+ ethernet switch background& F& \4 p% j% o2 P, p8 Y
At least 3-year+ experience on digital design and verification
; [7 e7 c; B% e+ L, A+ [* CExperience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
5 [" k5 S4 r9 }4 }- yFamiliarity with transaction-level verification at higher-level of abstractions is plus.5 m( b6 {: D" }
Experiences in developing measurable verification plan.& U4 I. \( d8 p- K' ]8 J3 b
Proficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl. |
|