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Job Title  igital verification Engineer
- A: d" l- s; s4 j9 ?Job Category :Semiconductor3 Z0 H* Z5 n/ L! U1 {8 L3 r- E" U" W
Location : Singapore; A( U& G2 V% ^8 Z# N+ R2 W9 _
Job Type : Permanent0 y9 n. o" I; z3 m6 F( ?5 K' y
Job Description:
0 V& R0 m7 g6 r o7 f0 XLooking for SoC Verification Engineers Experienced in System Verilog Tools$ `: G7 x9 R0 }+ }6 j$ m1 J* @6 ~
) \ Q6 n+ G( n% n2 h2 zResponsibilities:
: c2 [# p* d [# Y& @3 V; \8 a8 S- OConstrained-Random Verification using SystemVerilog.
. t( G* O9 k* L1 D# ]& O0 fDevelop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.7 W8 a4 Y( P1 I% K6 q* k+ e) w
Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests
8 q$ V. g# @3 W$ z8 q5 W1 HDeveloping and reviewing test plans: h. ~3 m% u- R' F* w! {: N& H; \6 f# X
Write coverage monitors to evaluate the coverage of the DUT.
% v* t$ D6 O6 w) UFormal verification using SystemVerilog Assertion to verify SOC or IP is plus
% M5 s7 I) J' G# ]! M4 N; {% W |# N- n' {0 y
Requirements:7 b! b6 R$ F t4 R% b
>4+ ethernet switch background7 K: w* B# h5 S2 u& ~/ l2 s
At least 3-year+ experience on digital design and verification
% d3 ~/ K( p1 `6 w2 kExperience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
8 ?$ |1 l5 T! {( UFamiliarity with transaction-level verification at higher-level of abstractions is plus.6 J/ j5 c8 g3 W
Experiences in developing measurable verification plan.
& ]+ J2 b; ?( O6 ?Proficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl. |
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