VHDL新手上路，程序Bug請教

ultraman · 發表於 2013-10-18 21:15:06

一般dly'event and dly='1'是不能寫在case裡面嗎？
因編譯會出現以下訊息
Error (10822): HDL error at CUB.vhd(70): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 15 warnings
Info: Allocated 144 megabytes of memory during processing
Error: Processing ended: Fri Oct 18 21:24:23 2013
Error: Elapsed time: 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 2 errors, 15 warnings

程序如果寫的不好，可以幫我改寫，因是自學，所以比較少機會可以看到其它人的寫法！

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity CUB is
Port(
sv_ctrl,coll_manu,coll_auto,count_v2,T1I,T2I,dly:in std_logic;
count_clr,coll_up,coll,cold_pin,T1O,T2O:out std_logic
);
end CUB;

Architecture cub_arc of CUB is
signal d : std_logic_vector(2 downto 0);
Begin

proce1

rocess(coll_manu,coll_auto,count_v2)
Begin
if coll_auto='0' then
if coll_manu='0' then
if count_v2='1' then
count_clr<='1';
else
count_clr<='0';
end if;
coll_up<='0';
coll<='0';
cold_pin<='0';
end if;
end if;

if coll_auto='0' then
if coll_manu='1' then
if count_v2='1' then
count_clr<='1';
else
count_clr<='0';
end if;
coll_up<='1';
coll<='1';
cold_pin<='1';
end if;
end if;

if coll_auto='1' then
if coll_manu='0' then
if (sv_ctrl and count_v2)='1' then
case d is
when "000"=>
coll_up<='1';
T1O<='1';
d<=d+1;
when "001"=>
if T1I='1' then
T1O<='0';
coll<='1';
cold_pin<='1';
T2O<='1';
d<=d+1;
end if;
when "010"=>
if T2I='1' then
T2O<='0';
coll_up<='0';
coll<='0';
cold_pin<='0';
d<=d+1;
end if;
when "011"=>
if (dly'event and dly='1') then
d<=d+1;
end if;
when "110"=>
count_clr<='1';
d<=d+1;
when "111"=>
if count_v2='0' then
count_clr<='0';
d<="000";
end if;
when others=>null;
end case;
end if;
end if;
end if;

if coll_auto='1' then
if coll_manu='1' then
coll_up<='0';
coll<='0';
cold_pin<='0';
end if;
end if;
end process proce1;

end cub_arc;

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