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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~" b- w# m" H9 I% v) h
想請問一下大家!!% i o% l, T% J. ~3 B6 y) m j( A
該怎麼設計?' W2 @/ F& ]& m" t
以下是我需要的功能~ e2 l9 e7 _- s: U
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | , l$ c0 ?) L# C- L1 q- q+ j
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Thereare 5 pipe stages in our pipelining design.
1 y. u7 e) T) C) X' ]It means that the input data can beobserved at the output port after 5 clock cycles.
" M2 `4 q* K# ?% YAll the stages must be readyto proceed at the same time.
$ \& p% y7 `. ?4 Z) ^When d_full is active, you have to keep the outputdata until d_full is disabled.
+ o: y7 v. h2 ~4 c6 ^7 O/ fIf d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. : t( f7 j4 f L
The pipeline bubbles haveto be eliminated when d_full is active.' [8 l. Q9 j2 T& K) Y3 t1 @# x
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