[急]verilog pipeline bubble 設計

HsuanChihCh@FB

我目前在設計一個pipeline的電路，且有防bubble機制，但在設計的過程中有些問題~
3 o5 h; b7 b! s, {$ m想請問一下大家!!
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以下是我需要的功能~
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Module name	my_pipeline
Signal	Direction	Description
clk	input	System clock
rst_n	input	reset signal, active low
d_in[15:0]	input	DUT input data
d_rdy	input	DUT input data ready
d_full	input	The next stage data full signal
pp_d[15:0]	output	DUT output data
pp_rdy	output	DUT output data ready
pp_full	output	DUT full signal to preceding stage

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Thereare 5 pipe stages in our pipelining design.
# ~; }* w; y0 ~4 ^It means that the input data can beobserved at the output port after 5 clock cycles.
All the stages must be readyto proceed at the same time.
7 t  Z; Z; b7 @* b: H: U! mWhen d_full is active, you have to keep the outputdata until d_full is disabled.
1 t: z0 Z$ F3 z8 UIf d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
: \' _; n7 f6 k8 w$ _5 rThe pipeline bubbles haveto be eliminated when d_full is active.
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