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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~
4 t) m* W6 U5 i/ c5 V想請問一下大家!!
4 V7 N# Q# Q2 P# N. n( s該怎麼設計?8 v7 O3 _1 Y4 ?3 {9 g
以下是我需要的功能~
! s; Z1 o- o) b4 \: z | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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( _; e# t; V; n: \# O$ tThereare 5 pipe stages in our pipelining design. O& n' E2 c: g+ ~3 v* b
It means that the input data can beobserved at the output port after 5 clock cycles. 9 @) f! M( h |1 G# `
All the stages must be readyto proceed at the same time. : }$ X+ Q0 ?2 B o$ t8 |
When d_full is active, you have to keep the outputdata until d_full is disabled. 0 l+ r3 G2 t8 }- V2 U6 U$ ]
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. & w7 d4 V/ r" k* c8 h4 b- C5 b
The pipeline bubbles haveto be eliminated when d_full is active.4 f" i' F; Q+ L, F
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