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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~
$ k5 |$ }: E/ S; L4 q2 e想請問一下大家!!
b+ @0 i: ^1 U該怎麼設計?2 @( G3 s+ N, M% u6 f
以下是我需要的功能~$ L4 ]# B! D8 f! B; L) H
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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2 J Z3 e* `& } AThereare 5 pipe stages in our pipelining design. ; V; d& P& m/ f$ { i
It means that the input data can beobserved at the output port after 5 clock cycles.
6 m% E/ ?1 @2 Y6 r+ h1 OAll the stages must be readyto proceed at the same time.
0 [( V! h: _+ UWhen d_full is active, you have to keep the outputdata until d_full is disabled. 7 I- u7 _7 Y* ~. u
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
8 Q" l" s6 _3 i$ D+ m9 r1 sThe pipeline bubbles haveto be eliminated when d_full is active.
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