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回復 4# 的帖子
1. Using technology file to create a library
: G" S! u* V% j+ N8 M8 ~ n0 H2 b2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.
% Y4 |1 R9 W# C8 l+ [3. Open new created library, and create some metal blockage if need.! i0 q9 ^/ q# Z+ @9 J
4. Do smash if need.
) _2 F( t+ {# s/ d/ X4 z& W4 G5. remove some unnecessary extension txst. IE VDD ---> VDD2 C$ g6 b- m `5 @/ S& R; j, U
6. Define power,ground as well as in/out port
# a4 O9 A! p# t% D7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.3 C7 T6 o- k3 B
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The processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.
6 p, l. z; y' t4 p8 R! c-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?
' B* ?$ p# ]. \( z1 S! a, oI don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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