用verilog撰寫取對數log電路

kevin

欲求A=Log(X),X為整數.A為fixed point.
" m- M: C* B: B) ?+ q$ j1 AX 先normalized to 0.5~1的範圍.即X = a x 2^n (a = 0.5~1)
5 `5 G' E) C9 k4 W. ]: {% w  u% D7 G再令a=1-h
5 x) X/ W9 M/ z  P2 V則A=Log(X)=n*Log(2)+Log(a)
& v8 X7 n2 o5 F' U          =n*Log(2)-(h+h^2/2+h^3/3+h^4/4+ ....)------->>此為泰勒級數展開.
可參考一下verilog code.
7 C1 |0 u* N+ l" E/ {

kevin

input X=20'b00000000000000000001
output Z=20'b00000000000000000101
8 p5 u+ Z% g4 F* _7 L輸出格式要看成XXXX.XXXXXXXXXXXXXXXX  Fixed Point Value,就是Q4.16格式
20'b00000000000000000101---->>代表0.0000762939453125,因為泰勒級數有限項數,不會為0.只是近似吧