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請問各位大大
' F# O/ m3 E' H1 O5 e) X( _1 ]+ F我用TSMC18的design kit作cell-based layout的練習,軟體是用encounter,大部分的步驟是依照CIC所提供的Lab去做,完成之後用我的GDS檔去做DRC,會出現下列的DRC ERROR,而且是M1~M5、via1~via5都會有這方面的error,因為error的數目頗大,不太可能用人工去debug,所以我想請問有經驗的大大們,能不能告訴我最大的問題點在哪裡?以及這些錯誤代表什麼?要如何debug比較適合?
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4 Z; c3 ]9 O7 ^ g先謝謝各位大大了!!感激不盡!!$ N7 ^$ J; k2 C* A: E4 C
$ f9 h$ J2 ^+ B( R1. M2.W.1 { @ M2 width < 0.28
$ b: W! l' l) o+ V/ J+ j7 i INT M2 < 0.28 SINGULAR REGION ABUT < 906 ^+ u4 Y! |* U7 ?
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2. M2.S.1 { @ M2 spacing < 0.28
* e H: |% e: E& r: x; w EXT M2 < 0.28 ABUT < 90 SINGULAR REGION' Z: Y8 X& j$ E
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3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um( R. U, }: o4 q, n. }
M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
' G- k1 B& ^# q- P U) D M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5" K& {8 U8 O! g. G) h+ B
M2_Wide = M2_G5 AND M2, Q. g+ x7 O) z9 u3 \
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M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
; D. e, X, X9 C7 }) B" D9 s, Q M2_Branch = M2_Exp NOT M2_Wide! F! K* |/ Z/ h/ I# z: S P
M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2% N5 `' i: A( L! ?6 g
M2_Check = M2 AND (SIZE M2_Exp BY 0.6)! C% p) ]$ f! J: b, E
M2_Else = M2_Check NOT INTERACT M2_Exp5 m6 G6 L# X5 \
M2_Extend = M2_Check NOT M2_Exp
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* W6 s8 i* T! a# \ EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
) w, \$ g- u+ _ EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
7 Y5 T3 d7 C+ W# `8 } EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
/ ?( v3 d& a- M+ r% s/ F: n0 v2 h3 W EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION8 N* B5 j. J* c7 Z
A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
$ b% h: `5 m! @3 z5 a A NOT INTERACT M2_Extend t- K1 W* _. C: E% @: k5 @* `
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. ]# {2 v2 S" i5 X4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um% e$ d; _7 m7 g/ p- d7 y
ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR # r9 {6 D7 B: w( @
VIA1 NOT M2
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/ T& f" L: G, D; u, p! T5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um. ?" {" `/ E) @7 q3 B
X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE // a narrow side
# K4 z3 T5 ~, S* o INT X < 0.26 ABUT == 90 INTERSECTING ONLY // adjacent narrow sides7 V% f: E5 D0 d. o9 B9 Z
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1 |% E5 q+ }: B- P; O6 \) ]7 _0 f6. M2.A.1{ @ Min M2 area region < 0.202
9 z; {- m: B' s) P' P AREA M2 < 0.202: q. y! ~3 t2 C( q$ h
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9 m0 w; A4 @- {! K @4 O0 m6 ~// Density check M2.R.1 included at the end of this file7 t" g+ _6 D& g2 `5 H% h* [
// VIA2 checks
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7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um! a0 E" c' s' y6 e& f4 U
A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY& p2 ^# B6 \7 f- Z P. c; i
A OUTSIDE RNGX // exclude from metal fuse protection ring area
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8. VIA2.S.1 { @ VIA2 SPACING < 0.26
& l; H& Q K# l, a. f EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION x) `- O( H. y" n9 J
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* S" B- y" r* z) }9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um" u* J, S$ p: T3 o1 n
ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
. Z. `& a9 \0 q VIA2 NOT M2
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10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um5 A0 @- |/ V# l3 f$ _$ L! v
X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE // a narrow side
% [* i5 E5 W7 c$ h6 c5 d INT X < 0.26 ABUT == 90 INTERSECTING ONLY // adjacent narrow sides
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