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LOAD SDC FILE時- s1 U i6 D+ J" N* @- f
Astro 訊息
* Q3 s9 U& K( m( C0 r$ ^) f---------------------------------------------------------------------------
, _1 s3 b1 I3 k6 ZInfo: starting Tcl processing' O# U: F2 p( o. N
Info: building design object name tables
8 ] W6 A' p' Q9 k+ O2 _Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
/ H" V8 X2 E& GWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004). s/ F3 q) E% O$ v. X7 m
# n. \: I9 E k* ?" ]- W----------------------------------------------------------------------------
! L3 n5 b j2 [, fSDC FILE
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2 _" i2 R: ^( `- [" [* p% M; Bset_multicycle_path 9 -through [list [get_pins \
3 O2 t. v" d4 c2 q3 ]2 o& i{TOP/test/mul/A[26]}] [get_pins \
2 U+ M# a4 s8 I2 Z) b{TOP/test/mul/A[25]}] [get_pins \
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-----------------------------------------------------------------------------, Z% e% r! x& {" B) d% `
Verilog File" f4 z% C, X) u+ [$ }, J; b& \
/ e0 `$ A, T# H0 f uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(4 [3 D1 b0 `" f2 R" N
icwAeYfNum[18:0]), .C(ae_avg) ); |
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